devices.py (11756:0d38e56356c7) devices.py (11936:8ab45fd19f40)
1# Copyright (c) 2016 ARM Limited
1# Copyright (c) 2016-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../')
44from common.Caches import *
45from common import CpuConfig
46
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../')
44from common.Caches import *
45from common import CpuConfig
46
47have_kvm = "kvm" in CpuConfig.cpu_names()
48
47class L1I(L1_ICache):
48 tag_latency = 1
49 data_latency = 1
50 response_latency = 1
51 mshrs = 4
52 tgts_per_mshr = 8
53 size = '48kB'
54 assoc = 3

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165class AtomicCluster(CpuCluster):
166 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
167 cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
168 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
169 cpu_voltage, *cpu_config)
170 def addL1(self):
171 pass
172
49class L1I(L1_ICache):
50 tag_latency = 1
51 data_latency = 1
52 response_latency = 1
53 mshrs = 4
54 tgts_per_mshr = 8
55 size = '48kB'
56 assoc = 3

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167class AtomicCluster(CpuCluster):
168 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
169 cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
170 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
171 cpu_voltage, *cpu_config)
172 def addL1(self):
173 pass
174
175class KvmCluster(CpuCluster):
176 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
177 cpu_config = [ CpuConfig.get("kvm"), None, None, None, None ]
178 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
179 cpu_voltage, *cpu_config)
180 def addL1(self):
181 pass
173
182
183
174class SimpleSystem(LinuxArmSystem):
175 cache_line_size = 64
176
177 def __init__(self, caches, mem_size, **kwargs):
178 super(SimpleSystem, self).__init__(**kwargs)
179
180 self.voltage_domain = VoltageDomain(voltage="1.0V")
181 self.clk_domain = SrcClockDomain(clock="1GHz",

--- 91 unchanged lines hidden --- 		184class SimpleSystem(LinuxArmSystem):
185 cache_line_size = 64
186
187 def __init__(self, caches, mem_size, **kwargs):
188 super(SimpleSystem, self).__init__(**kwargs)
189
190 self.voltage_domain = VoltageDomain(voltage="1.0V")
191 self.clk_domain = SrcClockDomain(clock="1GHz",

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