| devices.py (11722:f15f02d8c79e) | devices.py (11756:0d38e56356c7) |
|---|---|
| 1# Copyright (c) 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 160 unchanged lines hidden (view full) --- 169 cpu_voltage, *cpu_config) 170 def addL1(self): 171 pass 172 173 174class SimpleSystem(LinuxArmSystem): 175 cache_line_size = 64 176 | 1# Copyright (c) 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 160 unchanged lines hidden (view full) --- 169 cpu_voltage, *cpu_config) 170 def addL1(self): 171 pass 172 173 174class SimpleSystem(LinuxArmSystem): 175 cache_line_size = 64 176 |
| 177 def __init__(self, **kwargs): | 177 def __init__(self, caches, mem_size, **kwargs): |
| 178 super(SimpleSystem, self).__init__(**kwargs) 179 180 self.voltage_domain = VoltageDomain(voltage="1.0V") 181 self.clk_domain = SrcClockDomain(clock="1GHz", 182 voltage_domain=Parent.voltage_domain) 183 184 self.realview = VExpress_GEM5_V1() 185 --- 5 unchanged lines hidden (view full) --- 191 self.intrctrl = IntrControl() 192 self.terminal = Terminal() 193 self.vncserver = VncServer() 194 195 self.iobus = IOXBar() 196 # CPUs->PIO 197 self.iobridge = Bridge(delay='50ns') 198 # Device DMA -> MEM | 178 super(SimpleSystem, self).__init__(**kwargs) 179 180 self.voltage_domain = VoltageDomain(voltage="1.0V") 181 self.clk_domain = SrcClockDomain(clock="1GHz", 182 voltage_domain=Parent.voltage_domain) 183 184 self.realview = VExpress_GEM5_V1() 185 --- 5 unchanged lines hidden (view full) --- 191 self.intrctrl = IntrControl() 192 self.terminal = Terminal() 193 self.vncserver = VncServer() 194 195 self.iobus = IOXBar() 196 # CPUs->PIO 197 self.iobridge = Bridge(delay='50ns') 198 # Device DMA -> MEM |
| 199 self.dmabridge = Bridge(delay='50ns', 200 ranges=self.realview._mem_regions) | 199 mem_range = self.realview._mem_regions[0] 200 mem_range_size = long(mem_range[1]) - long(mem_range[0]) 201 assert mem_range_size >= long(Addr(mem_size)) 202 self._mem_range = AddrRange(start=mem_range[0], size=mem_size) 203 self._caches = caches 204 if self._caches: 205 self.iocache = IOCache(addr_ranges=[self._mem_range]) 206 else: 207 self.dmabridge = Bridge(delay='50ns', 208 ranges=[self._mem_range]) |
| 201 202 self._pci_devices = 0 203 self._clusters = [] 204 self._num_cpus = 0 205 206 def attach_pci(self, dev): 207 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) 208 self._pci_devices += 1 209 self.realview.attachPciDevice(dev, self.iobus) 210 211 def connect(self): 212 self.iobridge.master = self.iobus.slave 213 self.iobridge.slave = self.membus.master 214 | 209 210 self._pci_devices = 0 211 self._clusters = [] 212 self._num_cpus = 0 213 214 def attach_pci(self, dev): 215 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) 216 self._pci_devices += 1 217 self.realview.attachPciDevice(dev, self.iobus) 218 219 def connect(self): 220 self.iobridge.master = self.iobus.slave 221 self.iobridge.slave = self.membus.master 222 |
| 215 self.dmabridge.master = self.membus.slave 216 self.dmabridge.slave = self.iobus.master | 223 if self._caches: 224 self.iocache.mem_side = self.membus.slave 225 self.iocache.cpu_side = self.iobus.master 226 else: 227 self.dmabridge.master = self.membus.slave 228 self.dmabridge.slave = self.iobus.master |
| 217 218 self.gic_cpu_addr = self.realview.gic.cpu_addr 219 self.realview.attachOnChipIO(self.membus, self.iobridge) 220 self.realview.attachIO(self.iobus) 221 self.system_port = self.membus.slave 222 223 def numCpuClusters(self): 224 return len(self._clusters) --- 36 unchanged lines hidden --- | 229 230 self.gic_cpu_addr = self.realview.gic.cpu_addr 231 self.realview.attachOnChipIO(self.membus, self.iobridge) 232 self.realview.attachIO(self.iobus) 233 self.system_port = self.membus.slave 234 235 def numCpuClusters(self): 236 return len(self._clusters) --- 36 unchanged lines hidden --- |