devices.py (11569:2eae1dfaa791) devices.py (11630:6e2408ad4425)
1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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37# Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../common')
44from Caches import *
1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 28 unchanged lines hidden (view full) ---

37# Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../common')
44from Caches import *
45import CpuConfig
45
46class L1I(L1_ICache):
47 hit_latency = 1
48 response_latency = 1
49 mshrs = 4
50 tgts_per_mshr = 8
51 size = '48kB'
52 assoc = 3

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93 clusivity='mostly_excl'
94
95
96class MemBus(SystemXBar):
97 badaddr_responder = BadAddr(warn_access="warn")
98 default = Self.badaddr_responder.pio
99
100
46
47class L1I(L1_ICache):
48 hit_latency = 1
49 response_latency = 1
50 mshrs = 4
51 tgts_per_mshr = 8
52 size = '48kB'
53 assoc = 3

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94 clusivity='mostly_excl'
95
96
97class MemBus(SystemXBar):
98 badaddr_responder = BadAddr(warn_access="warn")
99 default = Self.badaddr_responder.pio
100
101
102class CpuCluster(SubSystem):
103 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage,
104 cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
105 super(CpuCluster, self).__init__()
106 self._cpu_type = cpu_type
107 self._l1i_type = l1i_type
108 self._l1d_type = l1d_type
109 self._wcache_type = wcache_type
110 self._l2_type = l2_type
111
112 assert num_cpus > 0
113
114 self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
115 self.clk_domain = SrcClockDomain(clock=cpu_clock,
116 voltage_domain=self.voltage_domain)
117
118 self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
119 clk_domain=self.clk_domain)
120 for idx in range(num_cpus) ]
121
122 for cpu in self.cpus:
123 cpu.createThreads()
124 cpu.createInterruptController()
125 cpu.socket_id = system.numCpuClusters()
126 system.addCpuCluster(self, num_cpus)
127
128 def requireCaches(self):
129 return self._cpu_type.require_caches()
130
131 def memoryMode(self):
132 return self._cpu_type.memory_mode()
133
134 def addL1(self):
135 for cpu in self.cpus:
136 l1i = None if self._l1i_type is None else self._l1i_type()
137 l1d = None if self._l1d_type is None else self._l1d_type()
138 iwc = None if self._wcache_type is None else self._wcache_type()
139 dwc = None if self._wcache_type is None else self._wcache_type()
140 cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
141
142 def addL2(self, clk_domain):
143 if self._l2_type is None:
144 return
145 self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
146 self.l2 = self._l2_type()
147 for cpu in self.cpus:
148 cpu.connectAllPorts(self.toL2Bus)
149 self.toL2Bus.master = self.l2.cpu_side
150
151 def connectMemSide(self, bus):
152 bus.slave
153 try:
154 self.l2.mem_side = bus.slave
155 except AttributeError:
156 for cpu in self.cpus:
157 cpu.connectAllPorts(bus)
158
159
160class AtomicCluster(CpuCluster):
161 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
162 cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
163 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
164 cpu_voltage, *cpu_config)
165 def addL1(self):
166 pass
167
168
101class SimpleSystem(LinuxArmSystem):
102 cache_line_size = 64
103
169class SimpleSystem(LinuxArmSystem):
170 cache_line_size = 64
171
104 voltage_domain = VoltageDomain(voltage="1.0V")
105 clk_domain = SrcClockDomain(clock="1GHz",
106 voltage_domain=Parent.voltage_domain)
172 def __init__(self, **kwargs):
173 super(SimpleSystem, self).__init__(**kwargs)
107
174
108 realview = VExpress_GEM5_V1()
175 self.voltage_domain = VoltageDomain(voltage="1.0V")
176 self.clk_domain = SrcClockDomain(clock="1GHz",
177 voltage_domain=Parent.voltage_domain)
109
178
110 gic_cpu_addr = realview.gic.cpu_addr
111 flags_addr = realview.realview_io.pio_addr + 0x30
179 self.realview = VExpress_GEM5_V1()
112
180
113 membus = MemBus()
181 self.gic_cpu_addr = self.realview.gic.cpu_addr
182 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
114
183
115 intrctrl = IntrControl()
116 terminal = Terminal()
117 vncserver = VncServer()
184 self.membus = MemBus()
118
185
119 iobus = IOXBar()
120 # CPUs->PIO
121 iobridge = Bridge(delay='50ns')
122 # Device DMA -> MEM
123 dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
186 self.intrctrl = IntrControl()
187 self.terminal = Terminal()
188 self.vncserver = VncServer()
124
189
125 _pci_devices = 0
126 _clusters = []
127 _cpus = []
190 self.iobus = IOXBar()
191 # CPUs->PIO
192 self.iobridge = Bridge(delay='50ns')
193 # Device DMA -> MEM
194 self.dmabridge = Bridge(delay='50ns',
195 ranges=self.realview._mem_regions)
128
196
197 self._pci_devices = 0
198 self._clusters = []
199 self._num_cpus = 0
200
129 def attach_pci(self, dev):
130 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
131 self._pci_devices += 1
132 self.realview.attachPciDevice(dev, self.iobus)
133
134 def connect(self):
135 self.iobridge.master = self.iobus.slave
136 self.iobridge.slave = self.membus.master
137
138 self.dmabridge.master = self.membus.slave
139 self.dmabridge.slave = self.iobus.master
140
141 self.gic_cpu_addr = self.realview.gic.cpu_addr
142 self.realview.attachOnChipIO(self.membus, self.iobridge)
143 self.realview.attachIO(self.iobus)
144 self.system_port = self.membus.slave
201 def attach_pci(self, dev):
202 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
203 self._pci_devices += 1
204 self.realview.attachPciDevice(dev, self.iobus)
205
206 def connect(self):
207 self.iobridge.master = self.iobus.slave
208 self.iobridge.slave = self.membus.master
209
210 self.dmabridge.master = self.membus.slave
211 self.dmabridge.slave = self.iobus.master
212
213 self.gic_cpu_addr = self.realview.gic.cpu_addr
214 self.realview.attachOnChipIO(self.membus, self.iobridge)
215 self.realview.attachIO(self.iobus)
216 self.system_port = self.membus.slave
217
218 def numCpuClusters(self):
219 return len(self._clusters)
220
221 def addCpuCluster(self, cpu_cluster, num_cpus):
222 assert cpu_cluster not in self._clusters
223 assert num_cpus > 0
224 self._clusters.append(cpu_cluster)
225 self._num_cpus += num_cpus
226
227 def numCpus(self):
228 return self._num_cpus
229
230 def addCaches(self, need_caches, last_cache_level):
231 if not need_caches:
232 # connect each cluster to the memory hierarchy
233 for cluster in self._clusters:
234 cluster.connectMemSide(self.membus)
235 return
236
237 cluster_mem_bus = self.membus
238 assert last_cache_level >= 1 and last_cache_level <= 3
239 for cluster in self._clusters:
240 cluster.addL1()
241 if last_cache_level > 1:
242 for cluster in self._clusters:
243 cluster.addL2(cluster.clk_domain)
244 if last_cache_level > 2:
245 max_clock_cluster = max(self._clusters,
246 key=lambda c: c.clk_domain.clock[0])
247 self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
248 self.toL3Bus = L2XBar(width=64)
249 self.toL3Bus.master = self.l3.cpu_side
250 self.l3.mem_side = self.membus.slave
251 cluster_mem_bus = self.toL3Bus
252
253 # connect each cluster to the memory hierarchy
254 for cluster in self._clusters:
255 cluster.connectMemSide(cluster_mem_bus)