1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37# Gabor Dozsa 38 39# System components used by the bigLITTLE.py configuration script 40 41from __future__ import print_function 42from __future__ import absolute_import 43 44import m5 45from m5.objects import * 46m5.util.addToPath('../../') 47from common.Caches import * 48from common import CpuConfig 49 50have_kvm = "ArmV8KvmCPU" in CpuConfig.cpu_names() 51 52class L1I(L1_ICache): 53 tag_latency = 1 54 data_latency = 1 55 response_latency = 1 56 mshrs = 4 57 tgts_per_mshr = 8 58 size = '48kB' 59 assoc = 3 60 61 62class L1D(L1_DCache): 63 tag_latency = 2 64 data_latency = 2 65 response_latency = 1 66 mshrs = 16 67 tgts_per_mshr = 16 68 size = '32kB' 69 assoc = 2 70 write_buffers = 16 71 72 73class WalkCache(PageTableWalkerCache): 74 tag_latency = 4 75 data_latency = 4 76 response_latency = 4 77 mshrs = 6 78 tgts_per_mshr = 8 79 size = '1kB' 80 assoc = 8 81 write_buffers = 16 82 83 84class L2(L2Cache): 85 tag_latency = 12 86 data_latency = 12 87 response_latency = 5 88 mshrs = 32 89 tgts_per_mshr = 8 90 size = '1MB' 91 assoc = 16 92 write_buffers = 8 93 clusivity='mostly_excl' 94 95 96class L3(Cache): 97 size = '16MB' 98 assoc = 16 99 tag_latency = 20 100 data_latency = 20 101 response_latency = 20 102 mshrs = 20 103 tgts_per_mshr = 12 104 clusivity='mostly_excl' 105 106 107class MemBus(SystemXBar): 108 badaddr_responder = BadAddr(warn_access="warn") 109 default = Self.badaddr_responder.pio 110 111 112class CpuCluster(SubSystem): 113 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage, 114 cpu_type, l1i_type, l1d_type, wcache_type, l2_type): 115 super(CpuCluster, self).__init__() 116 self._cpu_type = cpu_type 117 self._l1i_type = l1i_type 118 self._l1d_type = l1d_type 119 self._wcache_type = wcache_type 120 self._l2_type = l2_type 121 122 assert num_cpus > 0 123 124 self.voltage_domain = VoltageDomain(voltage=cpu_voltage) 125 self.clk_domain = SrcClockDomain(clock=cpu_clock, 126 voltage_domain=self.voltage_domain) 127 128 self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx, 129 clk_domain=self.clk_domain) 130 for idx in range(num_cpus) ] 131 132 for cpu in self.cpus: 133 cpu.createThreads() 134 cpu.createInterruptController() 135 cpu.socket_id = system.numCpuClusters() 136 system.addCpuCluster(self, num_cpus) 137 138 def requireCaches(self): 139 return self._cpu_type.require_caches() 140 141 def memoryMode(self): 142 return self._cpu_type.memory_mode() 143 144 def addL1(self): 145 for cpu in self.cpus: 146 l1i = None if self._l1i_type is None else self._l1i_type() 147 l1d = None if self._l1d_type is None else self._l1d_type() 148 iwc = None if self._wcache_type is None else self._wcache_type() 149 dwc = None if self._wcache_type is None else self._wcache_type() 150 cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc) 151 152 def addL2(self, clk_domain): 153 if self._l2_type is None: 154 return 155 self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) 156 self.l2 = self._l2_type() 157 for cpu in self.cpus: 158 cpu.connectAllPorts(self.toL2Bus) 159 self.toL2Bus.master = self.l2.cpu_side 160 161 def connectMemSide(self, bus): 162 bus.slave 163 try: 164 self.l2.mem_side = bus.slave 165 except AttributeError: 166 for cpu in self.cpus: 167 cpu.connectAllPorts(bus) 168 169 170class AtomicCluster(CpuCluster): 171 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): 172 cpu_config = [ CpuConfig.get("AtomicSimpleCPU"), None, None, None, None ] 173 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock, 174 cpu_voltage, *cpu_config) 175 def addL1(self): 176 pass 177 178class KvmCluster(CpuCluster): 179 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): 180 cpu_config = [ CpuConfig.get("ArmV8KvmCPU"), None, None, None, None ] 181 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock, 182 cpu_voltage, *cpu_config) 183 def addL1(self): 184 pass 185 186 187class SimpleSystem(LinuxArmSystem): 188 cache_line_size = 64 189 190 def __init__(self, caches, mem_size, **kwargs): 191 super(SimpleSystem, self).__init__(**kwargs) 192 193 self.voltage_domain = VoltageDomain(voltage="1.0V") 194 self.clk_domain = SrcClockDomain(clock="1GHz", 195 voltage_domain=Parent.voltage_domain) 196 197 self.realview = VExpress_GEM5_V1() 198
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