1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 182 unchanged lines hidden (view full) --- 191 super(SimpleSystem, self).__init__(**kwargs) 192 193 self.voltage_domain = VoltageDomain(voltage="1.0V") 194 self.clk_domain = SrcClockDomain(clock="1GHz", 195 voltage_domain=Parent.voltage_domain) 196 197 self.realview = VExpress_GEM5_V1() 198 |
199 if hasattr(self.realview.gic, 'cpu_addr'): 200 self.gic_cpu_addr = self.realview.gic.cpu_addr |
201 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 202 203 self.membus = MemBus() 204 205 self.intrctrl = IntrControl() 206 self.terminal = Terminal() 207 self.vncserver = VncServer() 208 --- 26 unchanged lines hidden (view full) --- 235 236 if self._caches: 237 self.iocache.mem_side = self.membus.slave 238 self.iocache.cpu_side = self.iobus.master 239 else: 240 self.dmabridge.master = self.membus.slave 241 self.dmabridge.slave = self.iobus.master 242 |
243 if hasattr(self.realview.gic, 'cpu_addr'): 244 self.gic_cpu_addr = self.realview.gic.cpu_addr |
245 self.realview.attachOnChipIO(self.membus, self.iobridge) 246 self.realview.attachIO(self.iobus) 247 self.system_port = self.membus.slave 248 249 def numCpuClusters(self): 250 return len(self._clusters) 251 252 def addCpuCluster(self, cpu_cluster, num_cpus): --- 34 unchanged lines hidden --- |