177c177
< def __init__(self, **kwargs):
---
> def __init__(self, caches, mem_size, **kwargs):
199,200c199,208
< self.dmabridge = Bridge(delay='50ns',
< ranges=self.realview._mem_regions)
---
> mem_range = self.realview._mem_regions[0]
> mem_range_size = long(mem_range[1]) - long(mem_range[0])
> assert mem_range_size >= long(Addr(mem_size))
> self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
> self._caches = caches
> if self._caches:
> self.iocache = IOCache(addr_ranges=[self._mem_range])
> else:
> self.dmabridge = Bridge(delay='50ns',
> ranges=[self._mem_range])
215,216c223,228
< self.dmabridge.master = self.membus.slave
< self.dmabridge.slave = self.iobus.master
---
> if self._caches:
> self.iocache.mem_side = self.membus.slave
> self.iocache.cpu_side = self.iobus.master
> else:
> self.dmabridge.master = self.membus.slave
> self.dmabridge.slave = self.iobus.master