devices.py (12148:6d367c7fdb1d) | devices.py (12165:463d335724d7) |
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1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 30 unchanged lines hidden (view full) --- 39# System components used by the bigLITTLE.py configuration script 40 41import m5 42from m5.objects import * 43m5.util.addToPath('../../') 44from common.Caches import * 45from common import CpuConfig 46 | 1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 30 unchanged lines hidden (view full) --- 39# System components used by the bigLITTLE.py configuration script 40 41import m5 42from m5.objects import * 43m5.util.addToPath('../../') 44from common.Caches import * 45from common import CpuConfig 46 |
47have_kvm = "kvm" in CpuConfig.cpu_names() | 47have_kvm = "ArmV8KvmCPU" in CpuConfig.cpu_names() |
48 49class L1I(L1_ICache): 50 tag_latency = 1 51 data_latency = 1 52 response_latency = 1 53 mshrs = 4 54 tgts_per_mshr = 8 55 size = '48kB' --- 105 unchanged lines hidden (view full) --- 161 self.l2.mem_side = bus.slave 162 except AttributeError: 163 for cpu in self.cpus: 164 cpu.connectAllPorts(bus) 165 166 167class AtomicCluster(CpuCluster): 168 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): | 48 49class L1I(L1_ICache): 50 tag_latency = 1 51 data_latency = 1 52 response_latency = 1 53 mshrs = 4 54 tgts_per_mshr = 8 55 size = '48kB' --- 105 unchanged lines hidden (view full) --- 161 self.l2.mem_side = bus.slave 162 except AttributeError: 163 for cpu in self.cpus: 164 cpu.connectAllPorts(bus) 165 166 167class AtomicCluster(CpuCluster): 168 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): |
169 cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ] | 169 cpu_config = [ CpuConfig.get("AtomicSimpleCPU"), None, None, None, None ] |
170 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock, 171 cpu_voltage, *cpu_config) 172 def addL1(self): 173 pass 174 175class KvmCluster(CpuCluster): 176 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): | 170 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock, 171 cpu_voltage, *cpu_config) 172 def addL1(self): 173 pass 174 175class KvmCluster(CpuCluster): 176 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"): |
177 cpu_config = [ CpuConfig.get("kvm"), None, None, None, None ] | 177 cpu_config = [ CpuConfig.get("ArmV8KvmCPU"), None, None, None, None ] |
178 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock, 179 cpu_voltage, *cpu_config) 180 def addL1(self): 181 pass 182 183 184class SimpleSystem(LinuxArmSystem): 185 cache_line_size = 64 --- 97 unchanged lines hidden --- | 178 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock, 179 cpu_voltage, *cpu_config) 180 def addL1(self): 181 pass 182 183 184class SimpleSystem(LinuxArmSystem): 185 cache_line_size = 64 --- 97 unchanged lines hidden --- |