1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../common')
44from Caches import *
45
46class L1I(L1_ICache):
47 hit_latency = 1
48 response_latency = 1
49 mshrs = 4
50 tgts_per_mshr = 8
51 size = '48kB'
52 assoc = 3
53
54
55class L1D(L1_DCache):
56 hit_latency = 2
57 response_latency = 1
58 mshrs = 16
59 tgts_per_mshr = 16
60 size = '32kB'
61 assoc = 2
62 write_buffers = 16
63
64
65class WalkCache(PageTableWalkerCache):
66 hit_latency = 4
67 response_latency = 4
68 mshrs = 6
69 tgts_per_mshr = 8
70 size = '1kB'
71 assoc = 8
72 write_buffers = 16
73
74
75class L2(L2Cache):
76 hit_latency = 12
77 response_latency = 5
78 mshrs = 32
79 tgts_per_mshr = 8
80 size = '1MB'
81 assoc = 16
82 write_buffers = 8
83 clusivity='mostly_excl'
84
85
86class L3(Cache):
87 size = '16MB'
88 assoc = 16
89 hit_latency = 20
90 response_latency = 20
91 mshrs = 20
92 tgts_per_mshr = 12
93 clusivity='mostly_excl'
94
95
96class MemBus(SystemXBar):
97 badaddr_responder = BadAddr(warn_access="warn")
98 default = Self.badaddr_responder.pio
99
100
101class SimpleSystem(LinuxArmSystem):
102 cache_line_size = 64
103
104 voltage_domain = VoltageDomain(voltage="1.0V")
105 clk_domain = SrcClockDomain(clock="1GHz",
106 voltage_domain=Parent.voltage_domain)
107
108 realview = VExpress_GEM5_V1()
109
110 gic_cpu_addr = realview.gic.cpu_addr
111 flags_addr = realview.realview_io.pio_addr + 0x30
112
113 membus = MemBus()
114
115 intrctrl = IntrControl()
116 terminal = Terminal()
117 vncserver = VncServer()
118
119 iobus = IOXBar()
120 # CPUs->PIO
121 iobridge = Bridge(delay='50ns')
122 # Device DMA -> MEM
123 dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
124
125 _pci_devices = 0
126 _clusters = []
127 _cpus = []
128
129 def attach_pci(self, dev):
130 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
131 self._pci_devices += 1
132 self.realview.attachPciDevice(dev, self.iobus)
133
134 def connect(self):
135 self.iobridge.master = self.iobus.slave
136 self.iobridge.slave = self.membus.master
137
138 self.dmabridge.master = self.membus.slave
139 self.dmabridge.slave = self.iobus.master
140
141 self.gic_cpu_addr = self.realview.gic.cpu_addr
142 self.realview.attachOnChipIO(self.membus, self.iobridge)
143 self.realview.attachIO(self.iobus)
144 self.system_port = self.membus.slave
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../common')
44from Caches import *
45
46class L1I(L1_ICache):
47 hit_latency = 1
48 response_latency = 1
49 mshrs = 4
50 tgts_per_mshr = 8
51 size = '48kB'
52 assoc = 3
53
54
55class L1D(L1_DCache):
56 hit_latency = 2
57 response_latency = 1
58 mshrs = 16
59 tgts_per_mshr = 16
60 size = '32kB'
61 assoc = 2
62 write_buffers = 16
63
64
65class WalkCache(PageTableWalkerCache):
66 hit_latency = 4
67 response_latency = 4
68 mshrs = 6
69 tgts_per_mshr = 8
70 size = '1kB'
71 assoc = 8
72 write_buffers = 16
73
74
75class L2(L2Cache):
76 hit_latency = 12
77 response_latency = 5
78 mshrs = 32
79 tgts_per_mshr = 8
80 size = '1MB'
81 assoc = 16
82 write_buffers = 8
83 clusivity='mostly_excl'
84
85
86class L3(Cache):
87 size = '16MB'
88 assoc = 16
89 hit_latency = 20
90 response_latency = 20
91 mshrs = 20
92 tgts_per_mshr = 12
93 clusivity='mostly_excl'
94
95
96class MemBus(SystemXBar):
97 badaddr_responder = BadAddr(warn_access="warn")
98 default = Self.badaddr_responder.pio
99
100
101class SimpleSystem(LinuxArmSystem):
102 cache_line_size = 64
103
104 voltage_domain = VoltageDomain(voltage="1.0V")
105 clk_domain = SrcClockDomain(clock="1GHz",
106 voltage_domain=Parent.voltage_domain)
107
108 realview = VExpress_GEM5_V1()
109
110 gic_cpu_addr = realview.gic.cpu_addr
111 flags_addr = realview.realview_io.pio_addr + 0x30
112
113 membus = MemBus()
114
115 intrctrl = IntrControl()
116 terminal = Terminal()
117 vncserver = VncServer()
118
119 iobus = IOXBar()
120 # CPUs->PIO
121 iobridge = Bridge(delay='50ns')
122 # Device DMA -> MEM
123 dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
124
125 _pci_devices = 0
126 _clusters = []
127 _cpus = []
128
129 def attach_pci(self, dev):
130 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
131 self._pci_devices += 1
132 self.realview.attachPciDevice(dev, self.iobus)
133
134 def connect(self):
135 self.iobridge.master = self.iobus.slave
136 self.iobridge.slave = self.membus.master
137
138 self.dmabridge.master = self.membus.slave
139 self.dmabridge.slave = self.iobus.master
140
141 self.gic_cpu_addr = self.realview.gic.cpu_addr
142 self.realview.attachOnChipIO(self.membus, self.iobridge)
143 self.realview.attachIO(self.iobus)
144 self.system_port = self.membus.slave