1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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169 cpu_voltage, *cpu_config)
170 def addL1(self):
171 pass
172
173
174class SimpleSystem(LinuxArmSystem):
175 cache_line_size = 64
176
177 def __init__(self, **kwargs):
178 super(SimpleSystem, self).__init__(**kwargs)
179
180 self.voltage_domain = VoltageDomain(voltage="1.0V")
181 self.clk_domain = SrcClockDomain(clock="1GHz",
182 voltage_domain=Parent.voltage_domain)
183
184 self.realview = VExpress_GEM5_V1()
185

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191 self.intrctrl = IntrControl()
192 self.terminal = Terminal()
193 self.vncserver = VncServer()
194
195 self.iobus = IOXBar()
196 # CPUs->PIO
197 self.iobridge = Bridge(delay='50ns')
198 # Device DMA -> MEM
199 self.dmabridge = Bridge(delay='50ns',
200 ranges=self.realview._mem_regions)
201
202 self._pci_devices = 0
203 self._clusters = []
204 self._num_cpus = 0
205
206 def attach_pci(self, dev):
207 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
208 self._pci_devices += 1
209 self.realview.attachPciDevice(dev, self.iobus)
210
211 def connect(self):
212 self.iobridge.master = self.iobus.slave
213 self.iobridge.slave = self.membus.master
214
215 self.dmabridge.master = self.membus.slave
216 self.dmabridge.slave = self.iobus.master
217
218 self.gic_cpu_addr = self.realview.gic.cpu_addr
219 self.realview.attachOnChipIO(self.membus, self.iobridge)
220 self.realview.attachIO(self.iobus)
221 self.system_port = self.membus.slave
222
223 def numCpuClusters(self):
224 return len(self._clusters)

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