1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 28 unchanged lines hidden (view full) ---

37# Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../common')
44from Caches import *
45
46class L1I(L1_ICache):
47 hit_latency = 1
48 response_latency = 1
49 mshrs = 4
50 tgts_per_mshr = 8
51 size = '48kB'
52 assoc = 3

--- 40 unchanged lines hidden (view full) ---

93 clusivity='mostly_excl'
94
95
96class MemBus(SystemXBar):
97 badaddr_responder = BadAddr(warn_access="warn")
98 default = Self.badaddr_responder.pio
99
100
101class SimpleSystem(LinuxArmSystem):
102 cache_line_size = 64
103
104 voltage_domain = VoltageDomain(voltage="1.0V")
105 clk_domain = SrcClockDomain(clock="1GHz",
106 voltage_domain=Parent.voltage_domain)
107
108 realview = VExpress_GEM5_V1()
109
110 gic_cpu_addr = realview.gic.cpu_addr
111 flags_addr = realview.realview_io.pio_addr + 0x30
112
113 membus = MemBus()
114
115 intrctrl = IntrControl()
116 terminal = Terminal()
117 vncserver = VncServer()
118
119 iobus = IOXBar()
120 # CPUs->PIO
121 iobridge = Bridge(delay='50ns')
122 # Device DMA -> MEM
123 dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
124
125 _pci_devices = 0
126 _clusters = []
127 _cpus = []
128
129 def attach_pci(self, dev):
130 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
131 self._pci_devices += 1
132 self.realview.attachPciDevice(dev, self.iobus)
133
134 def connect(self):
135 self.iobridge.master = self.iobus.slave
136 self.iobridge.slave = self.membus.master
137
138 self.dmabridge.master = self.membus.slave
139 self.dmabridge.slave = self.iobus.master
140
141 self.gic_cpu_addr = self.realview.gic.cpu_addr
142 self.realview.attachOnChipIO(self.membus, self.iobridge)
143 self.realview.attachIO(self.iobus)
144 self.system_port = self.membus.slave