| Caches.py (9310:aa7bf10e822a) | Caches.py (9315:2e00867b5001) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41from m5.objects import * 42 43# Base implementations of L1, L2, IO and TLB-walker caches. There are 44# used in the regressions and also as base components in the 45# system-configuration scripts. The values are meant to serve as a 46# starting point, and specific parameters can be overridden in the 47# specific instantiations. 48 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41from m5.objects import * 42 43# Base implementations of L1, L2, IO and TLB-walker caches. There are 44# used in the regressions and also as base components in the 45# system-configuration scripts. The values are meant to serve as a 46# starting point, and specific parameters can be overridden in the 47# specific instantiations. 48 |
| 49class L1(BaseCache): | 49class L1Cache(BaseCache): |
| 50 assoc = 2 51 hit_latency = 2 52 response_latency = 2 53 block_size = 64 54 mshrs = 4 55 tgts_per_mshr = 20 56 is_top_level = True 57 | 50 assoc = 2 51 hit_latency = 2 52 response_latency = 2 53 block_size = 64 54 mshrs = 4 55 tgts_per_mshr = 20 56 is_top_level = True 57 |
| 58class L2(BaseCache): | 58class L2Cache(BaseCache): |
| 59 assoc = 8 60 block_size = 64 61 hit_latency = 20 62 response_latency = 20 63 mshrs = 92 64 tgts_per_mshr = 16 65 write_buffers = 8 66 --- 12 unchanged lines hidden (view full) --- 79 assoc = 2 80 block_size = 64 81 hit_latency = 2 82 response_latency = 2 83 mshrs = 10 84 size = '1kB' 85 tgts_per_mshr = 12 86 is_top_level = True | 59 assoc = 8 60 block_size = 64 61 hit_latency = 20 62 response_latency = 20 63 mshrs = 92 64 tgts_per_mshr = 16 65 write_buffers = 8 66 --- 12 unchanged lines hidden (view full) --- 79 assoc = 2 80 block_size = 64 81 hit_latency = 2 82 response_latency = 2 83 mshrs = 10 84 size = '1kB' 85 tgts_per_mshr = 12 86 is_top_level = True |
| 87 | |