Caches.py (9263:066099902102) | Caches.py (9288:3d6da8559605) |
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1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Lisa Hsu 28 29from m5.objects import * 30 31class L1Cache(BaseCache): 32 assoc = 2 33 block_size = 64 | 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 38# 39# Authors: Lisa Hsu 40 41from m5.objects import * 42 43class L1Cache(BaseCache): 44 assoc = 2 45 block_size = 64 |
34 hit_latency = '1ns' 35 response_latency = '1ns' | 46 hit_latency = 2 47 response_latency = 2 |
36 mshrs = 10 37 tgts_per_mshr = 20 38 is_top_level = True 39 40class L2Cache(BaseCache): 41 assoc = 8 42 block_size = 64 | 48 mshrs = 10 49 tgts_per_mshr = 20 50 is_top_level = True 51 52class L2Cache(BaseCache): 53 assoc = 8 54 block_size = 64 |
43 hit_latency = '10ns' 44 response_latency = '10ns' | 55 hit_latency = 20 56 response_latency = 20 |
45 mshrs = 20 46 tgts_per_mshr = 12 47 48class PageTableWalkerCache(BaseCache): 49 assoc = 2 50 block_size = 64 | 57 mshrs = 20 58 tgts_per_mshr = 12 59 60class PageTableWalkerCache(BaseCache): 61 assoc = 2 62 block_size = 64 |
51 hit_latency = '1ns' 52 response_latency = '1ns' | 63 hit_latency = 2 64 response_latency = 2 |
53 mshrs = 10 54 size = '1kB' 55 tgts_per_mshr = 12 56 is_top_level = True 57 58class IOCache(BaseCache): 59 assoc = 8 60 block_size = 64 | 65 mshrs = 10 66 size = '1kB' 67 tgts_per_mshr = 12 68 is_top_level = True 69 70class IOCache(BaseCache): 71 assoc = 8 72 block_size = 64 |
61 hit_latency = '10ns' 62 response_latency = '10ns' | 73 hit_latency = 50 74 response_latency = 50 |
63 mshrs = 20 64 size = '1kB' 65 tgts_per_mshr = 12 66 forward_snoops = False 67 is_top_level = True | 75 mshrs = 20 76 size = '1kB' 77 tgts_per_mshr = 12 78 forward_snoops = False 79 is_top_level = True |