Caches.py (10887:279efb97ec99) Caches.py (11053:62544e45c0f4)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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41from m5.objects import *
42
43# Base implementations of L1, L2, IO and TLB-walker caches. There are
44# used in the regressions and also as base components in the
45# system-configuration scripts. The values are meant to serve as a
46# starting point, and specific parameters can be overridden in the
47# specific instantiations.
48
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 32 unchanged lines hidden (view full) ---

41from m5.objects import *
42
43# Base implementations of L1, L2, IO and TLB-walker caches. There are
44# used in the regressions and also as base components in the
45# system-configuration scripts. The values are meant to serve as a
46# starting point, and specific parameters can be overridden in the
47# specific instantiations.
48
49class L1Cache(BaseCache):
49class L1Cache(Cache):
50 assoc = 2
51 hit_latency = 2
52 response_latency = 2
53 mshrs = 4
54 tgts_per_mshr = 20
55
56class L1_ICache(L1Cache):
57 is_read_only = True
58
59class L1_DCache(L1Cache):
60 pass
61
50 assoc = 2
51 hit_latency = 2
52 response_latency = 2
53 mshrs = 4
54 tgts_per_mshr = 20
55
56class L1_ICache(L1Cache):
57 is_read_only = True
58
59class L1_DCache(L1Cache):
60 pass
61
62class L2Cache(BaseCache):
62class L2Cache(Cache):
63 assoc = 8
64 hit_latency = 20
65 response_latency = 20
66 mshrs = 20
67 tgts_per_mshr = 12
68 write_buffers = 8
69
63 assoc = 8
64 hit_latency = 20
65 response_latency = 20
66 mshrs = 20
67 tgts_per_mshr = 12
68 write_buffers = 8
69
70class IOCache(BaseCache):
70class IOCache(Cache):
71 assoc = 8
72 hit_latency = 50
73 response_latency = 50
74 mshrs = 20
75 size = '1kB'
76 tgts_per_mshr = 12
77 forward_snoops = False
78
71 assoc = 8
72 hit_latency = 50
73 response_latency = 50
74 mshrs = 20
75 size = '1kB'
76 tgts_per_mshr = 12
77 forward_snoops = False
78
79class PageTableWalkerCache(BaseCache):
79class PageTableWalkerCache(Cache):
80 assoc = 2
81 hit_latency = 2
82 response_latency = 2
83 mshrs = 10
84 size = '1kB'
85 tgts_per_mshr = 12
86 forward_snoops = False
87 # the x86 table walker actually writes to the table-walker cache
88 if buildEnv['TARGET_ISA'] == 'x86':
89 is_read_only = False
90 else:
91 is_read_only = True
80 assoc = 2
81 hit_latency = 2
82 response_latency = 2
83 mshrs = 10
84 size = '1kB'
85 tgts_per_mshr = 12
86 forward_snoops = False
87 # the x86 table walker actually writes to the table-walker cache
88 if buildEnv['TARGET_ISA'] == 'x86':
89 is_read_only = False
90 else:
91 is_read_only = True