| CacheConfig.py (9815:3b3b94536547) | CacheConfig.py (10405:7a618c07e663) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 57 unchanged lines hidden (view full) --- 66 # Provide a clock for the L2 and the L1-to-L2 bus here as they 67 # are not connected using addTwoLevelCacheHierarchy. Use the 68 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 69 # bytes (256 bits). 70 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 71 size=options.l2_size, 72 assoc=options.l2_assoc) 73 | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 57 unchanged lines hidden (view full) --- 66 # Provide a clock for the L2 and the L1-to-L2 bus here as they 67 # are not connected using addTwoLevelCacheHierarchy. Use the 68 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 69 # bytes (256 bits). 70 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 71 size=options.l2_size, 72 assoc=options.l2_assoc) 73 |
| 74 system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, 75 width = 32) | 74 system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain, 75 width = 32) |
| 76 system.l2.cpu_side = system.tol2bus.master 77 system.l2.mem_side = system.membus.slave 78 79 for i in xrange(options.num_cpus): 80 if options.caches: 81 icache = icache_class(size=options.l1i_size, 82 assoc=options.l1i_assoc) 83 dcache = dcache_class(size=options.l1d_size, --- 17 unchanged lines hidden --- | 76 system.l2.cpu_side = system.tol2bus.master 77 system.l2.mem_side = system.membus.slave 78 79 for i in xrange(options.num_cpus): 80 if options.caches: 81 icache = icache_class(size=options.l1i_size, 82 assoc=options.l1i_assoc) 83 dcache = dcache_class(size=options.l1d_size, --- 17 unchanged lines hidden --- |