CacheConfig.py (9789:233420718e61) CacheConfig.py (9793:6e6cefc1db1f)
1# Copyright (c) 2012 ARM Limited
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 49 unchanged lines hidden (view full) ---

59 dcache_class, icache_class, l2_cache_class = \
60 L1Cache, L1Cache, L2Cache
61
62 if options.l2cache:
63 # Provide a clock for the L2 and the L1-to-L2 bus here as they
64 # are not connected using addTwoLevelCacheHierarchy. Use the
65 # same clock as the CPUs, and set the L1-to-L2 bus width to 32
66 # bytes (256 bits).
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 49 unchanged lines hidden (view full) ---

59 dcache_class, icache_class, l2_cache_class = \
60 L1Cache, L1Cache, L2Cache
61
62 if options.l2cache:
63 # Provide a clock for the L2 and the L1-to-L2 bus here as they
64 # are not connected using addTwoLevelCacheHierarchy. Use the
65 # same clock as the CPUs, and set the L1-to-L2 bus width to 32
66 # bytes (256 bits).
67 system.l2 = l2_cache_class(clock=options.cpu_clock,
67 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
68 size=options.l2_size,
69 assoc=options.l2_assoc,
70 block_size=options.cacheline_size)
71
68 size=options.l2_size,
69 assoc=options.l2_assoc,
70 block_size=options.cacheline_size)
71
72 system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32)
72 system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
73 width = 32)
73 system.l2.cpu_side = system.tol2bus.master
74 system.l2.mem_side = system.membus.slave
75
76 for i in xrange(options.num_cpus):
77 if options.caches:
78 icache = icache_class(size=options.l1i_size,
79 assoc=options.l1i_assoc,
80 block_size=options.cacheline_size)

--- 19 unchanged lines hidden --- 		74 system.l2.cpu_side = system.tol2bus.master
75 system.l2.mem_side = system.membus.slave
76
77 for i in xrange(options.num_cpus):
78 if options.caches:
79 icache = icache_class(size=options.l1i_size,
80 assoc=options.l1i_assoc,
81 block_size=options.cacheline_size)

--- 19 unchanged lines hidden ---