CacheConfig.py (9284:f4ff625eae56) | CacheConfig.py (9522:9290a0198c50) |
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1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Lisa Hsu 28 29# Configure the M5 cache hierarchy config in one place 30# 31 32import m5 33from m5.objects import * 34from Caches import * | 13# Copyright (c) 2010 Advanced Micro Devices, Inc. 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 39# Authors: Lisa Hsu 40 41# Configure the M5 cache hierarchy config in one place 42# 43 44import m5 45from m5.objects import * 46from Caches import * |
35from O3_ARM_v7a import * | |
36 37def config_cache(options, system): | 47 48def config_cache(options, system): |
49 if options.cpu_type == "arm_detailed": 50 try: 51 from O3_ARM_v7a import * 52 except: 53 print "arm_detailed is unavailable. Did you compile the O3 model?" 54 sys.exit(1) 55 56 dcache_class, icache_class, l2_cache_class = \ 57 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 58 else: 59 dcache_class, icache_class, l2_cache_class = \ 60 L1Cache, L1Cache, L2Cache 61 |
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38 if options.l2cache: 39 # Provide a clock for the L2 and the L1-to-L2 bus here as they 40 # are not connected using addTwoLevelCacheHierarchy. Use the 41 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 42 # bytes (256 bits). | 62 if options.l2cache: 63 # Provide a clock for the L2 and the L1-to-L2 bus here as they 64 # are not connected using addTwoLevelCacheHierarchy. Use the 65 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 66 # bytes (256 bits). |
43 if options.cpu_type == "arm_detailed": 44 system.l2 = O3_ARM_v7aL2(clock = options.clock, 45 size = options.l2_size, 46 assoc = options.l2_assoc, 47 block_size=options.cacheline_size) 48 else: 49 system.l2 = L2Cache(clock = options.clock, 50 size = options.l2_size, 51 assoc = options.l2_assoc, 52 block_size = options.cacheline_size) | 67 system.l2 = l2_cache_class(clock=options.clock, 68 size=options.l2_size, 69 assoc=options.l2_assoc, 70 block_size=options.cacheline_size) |
53 54 system.tol2bus = CoherentBus(clock = options.clock, width = 32) 55 system.l2.cpu_side = system.tol2bus.master 56 system.l2.mem_side = system.membus.slave 57 58 for i in xrange(options.num_cpus): 59 if options.caches: | 71 72 system.tol2bus = CoherentBus(clock = options.clock, width = 32) 73 system.l2.cpu_side = system.tol2bus.master 74 system.l2.mem_side = system.membus.slave 75 76 for i in xrange(options.num_cpus): 77 if options.caches: |
60 if options.cpu_type == "arm_detailed": 61 icache = O3_ARM_v7a_ICache(size = options.l1i_size, 62 assoc = options.l1i_assoc, 63 block_size=options.cacheline_size) 64 dcache = O3_ARM_v7a_DCache(size = options.l1d_size, 65 assoc = options.l1d_assoc, 66 block_size=options.cacheline_size) 67 else: 68 icache = L1Cache(size = options.l1i_size, 69 assoc = options.l1i_assoc, 70 block_size=options.cacheline_size) 71 dcache = L1Cache(size = options.l1d_size, 72 assoc = options.l1d_assoc, 73 block_size=options.cacheline_size) | 78 icache = icache_class(size=options.l1i_size, 79 assoc=options.l1i_assoc, 80 block_size=options.cacheline_size) 81 dcache = dcache_class(size=options.l1d_size, 82 assoc=options.l1d_assoc, 83 block_size=options.cacheline_size) |
74 75 # When connecting the caches, the clock is also inherited 76 # from the CPU in question 77 if buildEnv['TARGET_ISA'] == 'x86': 78 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 79 PageTableWalkerCache(), 80 PageTableWalkerCache()) 81 else: 82 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 83 system.cpu[i].createInterruptController() 84 if options.l2cache: 85 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 86 else: 87 system.cpu[i].connectAllPorts(system.membus) 88 89 return system | 84 85 # When connecting the caches, the clock is also inherited 86 # from the CPU in question 87 if buildEnv['TARGET_ISA'] == 'x86': 88 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 89 PageTableWalkerCache(), 90 PageTableWalkerCache()) 91 else: 92 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 93 system.cpu[i].createInterruptController() 94 if options.l2cache: 95 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 96 else: 97 system.cpu[i].connectAllPorts(system.membus) 98 99 return system |