CacheConfig.py (9036:6385cf85bf12) | CacheConfig.py (9284:f4ff625eae56) |
---|---|
1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31 32import m5 33from m5.objects import * 34from Caches import * 35from O3_ARM_v7a import * 36 37def config_cache(options, system): 38 if options.l2cache: | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31 32import m5 33from m5.objects import * 34from Caches import * 35from O3_ARM_v7a import * 36 37def config_cache(options, system): 38 if options.l2cache: |
39 # Provide a clock for the L2 and the L1-to-L2 bus here as they 40 # are not connected using addTwoLevelCacheHierarchy. Use the 41 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 42 # bytes (256 bits). |
|
39 if options.cpu_type == "arm_detailed": | 43 if options.cpu_type == "arm_detailed": |
40 system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 41 block_size=options.cacheline_size) | 44 system.l2 = O3_ARM_v7aL2(clock = options.clock, 45 size = options.l2_size, 46 assoc = options.l2_assoc, 47 block_size=options.cacheline_size) |
42 else: | 48 else: |
43 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 44 block_size=options.cacheline_size) | 49 system.l2 = L2Cache(clock = options.clock, 50 size = options.l2_size, 51 assoc = options.l2_assoc, 52 block_size = options.cacheline_size) |
45 | 53 |
46 system.tol2bus = CoherentBus() | 54 system.tol2bus = CoherentBus(clock = options.clock, width = 32) |
47 system.l2.cpu_side = system.tol2bus.master 48 system.l2.mem_side = system.membus.slave 49 50 for i in xrange(options.num_cpus): 51 if options.caches: 52 if options.cpu_type == "arm_detailed": 53 icache = O3_ARM_v7a_ICache(size = options.l1i_size, | 55 system.l2.cpu_side = system.tol2bus.master 56 system.l2.mem_side = system.membus.slave 57 58 for i in xrange(options.num_cpus): 59 if options.caches: 60 if options.cpu_type == "arm_detailed": 61 icache = O3_ARM_v7a_ICache(size = options.l1i_size, |
54 assoc = options.l1i_assoc, 55 block_size=options.cacheline_size) | 62 assoc = options.l1i_assoc, 63 block_size=options.cacheline_size) |
56 dcache = O3_ARM_v7a_DCache(size = options.l1d_size, | 64 dcache = O3_ARM_v7a_DCache(size = options.l1d_size, |
57 assoc = options.l1d_assoc, 58 block_size=options.cacheline_size) | 65 assoc = options.l1d_assoc, 66 block_size=options.cacheline_size) |
59 else: 60 icache = L1Cache(size = options.l1i_size, 61 assoc = options.l1i_assoc, 62 block_size=options.cacheline_size) 63 dcache = L1Cache(size = options.l1d_size, 64 assoc = options.l1d_assoc, 65 block_size=options.cacheline_size) 66 | 67 else: 68 icache = L1Cache(size = options.l1i_size, 69 assoc = options.l1i_assoc, 70 block_size=options.cacheline_size) 71 dcache = L1Cache(size = options.l1d_size, 72 assoc = options.l1d_assoc, 73 block_size=options.cacheline_size) 74 |
75 # When connecting the caches, the clock is also inherited 76 # from the CPU in question |
|
67 if buildEnv['TARGET_ISA'] == 'x86': 68 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 69 PageTableWalkerCache(), 70 PageTableWalkerCache()) 71 else: 72 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 73 system.cpu[i].createInterruptController() 74 if options.l2cache: 75 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 76 else: 77 system.cpu[i].connectAllPorts(system.membus) 78 79 return system | 77 if buildEnv['TARGET_ISA'] == 'x86': 78 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 79 PageTableWalkerCache(), 80 PageTableWalkerCache()) 81 else: 82 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 83 system.cpu[i].createInterruptController() 84 if options.l2cache: 85 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 86 else: 87 system.cpu[i].connectAllPorts(system.membus) 88 89 return system |