CacheConfig.py (8863:50ce4deacda9) | CacheConfig.py (9036:6385cf85bf12) |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 29 unchanged lines hidden (view full) --- 38 if options.l2cache: 39 if options.cpu_type == "arm_detailed": 40 system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 41 block_size=options.cacheline_size) 42 else: 43 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 44 block_size=options.cacheline_size) 45 | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 29 unchanged lines hidden (view full) --- 38 if options.l2cache: 39 if options.cpu_type == "arm_detailed": 40 system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 41 block_size=options.cacheline_size) 42 else: 43 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 44 block_size=options.cacheline_size) 45 |
46 system.tol2bus = Bus() | 46 system.tol2bus = CoherentBus() |
47 system.l2.cpu_side = system.tol2bus.master 48 system.l2.mem_side = system.membus.slave 49 50 for i in xrange(options.num_cpus): 51 if options.caches: 52 if options.cpu_type == "arm_detailed": 53 icache = O3_ARM_v7a_ICache(size = options.l1i_size, 54 assoc = options.l1i_assoc, --- 25 unchanged lines hidden --- | 47 system.l2.cpu_side = system.tol2bus.master 48 system.l2.mem_side = system.membus.slave 49 50 for i in xrange(options.num_cpus): 51 if options.caches: 52 if options.cpu_type == "arm_detailed": 53 icache = O3_ARM_v7a_ICache(size = options.l1i_size, 54 assoc = options.l1i_assoc, --- 25 unchanged lines hidden --- |