CacheConfig.py (8846:2eaf1809c6c6) | CacheConfig.py (8863:50ce4deacda9) |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 65 block_size=options.cacheline_size) 66 67 if buildEnv['TARGET_ISA'] == 'x86': 68 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 69 PageTableWalkerCache(), 70 PageTableWalkerCache()) 71 else: 72 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 65 block_size=options.cacheline_size) 66 67 if buildEnv['TARGET_ISA'] == 'x86': 68 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 69 PageTableWalkerCache(), 70 PageTableWalkerCache()) 71 else: 72 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) |
73 system.cpu[i].createInterruptController() |
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73 if options.l2cache: 74 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 75 else: 76 system.cpu[i].connectAllPorts(system.membus) 77 78 return system | 74 if options.l2cache: 75 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 76 else: 77 system.cpu[i].connectAllPorts(system.membus) 78 79 return system |