CacheConfig.py (8724:7b4d80b26e35) | CacheConfig.py (8839:eeb293859255) |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 30 unchanged lines hidden (view full) --- 39 if options.cpu_type == "arm_detailed": 40 system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 41 block_size=options.cacheline_size) 42 else: 43 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 44 block_size=options.cacheline_size) 45 46 system.tol2bus = Bus() | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 30 unchanged lines hidden (view full) --- 39 if options.cpu_type == "arm_detailed": 40 system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 41 block_size=options.cacheline_size) 42 else: 43 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 44 block_size=options.cacheline_size) 45 46 system.tol2bus = Bus() |
47 system.l2.cpu_side = system.tol2bus.port 48 system.l2.mem_side = system.membus.port | 47 system.l2.cpu_side = system.tol2bus.master 48 system.l2.mem_side = system.membus.slave |
49 system.l2.num_cpus = options.num_cpus 50 51 for i in xrange(options.num_cpus): 52 if options.caches: 53 if options.cpu_type == "arm_detailed": 54 icache = O3_ARM_v7a_ICache(size = options.l1i_size, 55 assoc = options.l1i_assoc, 56 block_size=options.cacheline_size) --- 23 unchanged lines hidden --- | 49 system.l2.num_cpus = options.num_cpus 50 51 for i in xrange(options.num_cpus): 52 if options.caches: 53 if options.cpu_type == "arm_detailed": 54 icache = O3_ARM_v7a_ICache(size = options.l1i_size, 55 assoc = options.l1i_assoc, 56 block_size=options.cacheline_size) --- 23 unchanged lines hidden --- |