CacheConfig.py (8057:5a8208fa1600) | CacheConfig.py (8724:7b4d80b26e35) |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Lisa Hsu 28 29# Configure the M5 cache hierarchy config in one place 30# 31 32import m5 33from m5.objects import * 34from Caches import * | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Lisa Hsu 28 29# Configure the M5 cache hierarchy config in one place 30# 31 32import m5 33from m5.objects import * 34from Caches import * |
35from O3_ARM_v7a import * |
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35 36def config_cache(options, system): 37 if options.l2cache: | 36 37def config_cache(options, system): 38 if options.l2cache: |
38 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 39 block_size=options.cacheline_size) | 39 if options.cpu_type == "arm_detailed": 40 system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, 41 block_size=options.cacheline_size) 42 else: 43 system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, 44 block_size=options.cacheline_size) 45 |
40 system.tol2bus = Bus() 41 system.l2.cpu_side = system.tol2bus.port 42 system.l2.mem_side = system.membus.port 43 system.l2.num_cpus = options.num_cpus 44 45 for i in xrange(options.num_cpus): 46 if options.caches: | 46 system.tol2bus = Bus() 47 system.l2.cpu_side = system.tol2bus.port 48 system.l2.mem_side = system.membus.port 49 system.l2.num_cpus = options.num_cpus 50 51 for i in xrange(options.num_cpus): 52 if options.caches: |
47 icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, 48 block_size=options.cacheline_size) 49 dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, 50 block_size=options.cacheline_size) | 53 if options.cpu_type == "arm_detailed": 54 icache = O3_ARM_v7a_ICache(size = options.l1i_size, 55 assoc = options.l1i_assoc, 56 block_size=options.cacheline_size) 57 dcache = O3_ARM_v7a_DCache(size = options.l1d_size, 58 assoc = options.l1d_assoc, 59 block_size=options.cacheline_size) 60 else: 61 icache = L1Cache(size = options.l1i_size, 62 assoc = options.l1i_assoc, 63 block_size=options.cacheline_size) 64 dcache = L1Cache(size = options.l1d_size, 65 assoc = options.l1d_assoc, 66 block_size=options.cacheline_size) 67 |
51 if buildEnv['TARGET_ISA'] == 'x86': 52 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 53 PageTableWalkerCache(), 54 PageTableWalkerCache()) 55 else: 56 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 57 if options.l2cache: 58 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 59 else: 60 system.cpu[i].connectAllPorts(system.membus) 61 62 return system | 68 if buildEnv['TARGET_ISA'] == 'x86': 69 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 70 PageTableWalkerCache(), 71 PageTableWalkerCache()) 72 else: 73 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 74 if options.l2cache: 75 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 76 else: 77 system.cpu[i].connectAllPorts(system.membus) 78 79 return system |