CacheConfig.py (7868:6029008db669) | CacheConfig.py (7876:189b9b258779) |
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1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 38 unchanged lines hidden (view full) --- 47 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 48 L1Cache(size = '64kB'), 49 PageTableWalkerCache(), 50 PageTableWalkerCache()) 51 else: 52 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 53 L1Cache(size = '64kB')) 54 if options.l2cache: | 1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 38 unchanged lines hidden (view full) --- 47 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 48 L1Cache(size = '64kB'), 49 PageTableWalkerCache(), 50 PageTableWalkerCache()) 51 else: 52 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 53 L1Cache(size = '64kB')) 54 if options.l2cache: |
55 system.cpu[i].connectMemPorts(system.tol2bus) | 55 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) |
56 else: | 56 else: |
57 system.cpu[i].connectMemPorts(system.membus) | 57 system.cpu[i].connectAllPorts(system.membus) |
58 59 return system | 58 59 return system |