CacheConfig.py (13811:88827de8fced) CacheConfig.py (13876:1643f200987c)
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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42#
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import m5
48from m5.objects import *
49from .Caches import *
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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42#
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import m5
48from m5.objects import *
49from .Caches import *
50from . import HWPConfig
50
51def config_cache(options, system):
52 if options.external_memory_system and (options.caches or options.l2cache):
53 print("External caches and internal caches are exclusive options.\n")
54 sys.exit(1)
55
56 if options.external_memory_system:
57 ExternalCache = ExternalCacheFactory(options.external_memory_system)

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99 # same clock as the CPUs.
100 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
101 size=options.l2_size,
102 assoc=options.l2_assoc)
103
104 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
105 system.l2.cpu_side = system.tol2bus.master
106 system.l2.mem_side = system.membus.slave
51
52def config_cache(options, system):
53 if options.external_memory_system and (options.caches or options.l2cache):
54 print("External caches and internal caches are exclusive options.\n")
55 sys.exit(1)
56
57 if options.external_memory_system:
58 ExternalCache = ExternalCacheFactory(options.external_memory_system)

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100 # same clock as the CPUs.
101 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
102 size=options.l2_size,
103 assoc=options.l2_assoc)
104
105 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
106 system.l2.cpu_side = system.tol2bus.master
107 system.l2.mem_side = system.membus.slave
108 if options.l2_hwp_type:
109 hwpClass = HWPConfig.get(options.l2_hwp_type)
110 if system.l2.prefetcher != "Null":
111 print("Warning: l2-hwp-type is set (", hwpClass, "), but",
112 "the current l2 has a default Hardware Prefetcher",
113 "of type", type(system.l2.prefetcher), ", using the",
114 "specified by the flag option.")
115 system.l2.prefetcher = hwpClass()
107
108 if options.memchecker:
109 system.memchecker = MemChecker()
110
111 for i in range(options.num_cpus):
112 if options.caches:
113 icache = icache_class(size=options.l1i_size,
114 assoc=options.l1i_assoc)

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134 dcache_mon.memchecker = system.memchecker
135
136 # Connect monitor
137 dcache_mon.mem_side = dcache.cpu_side
138
139 # Let CPU connect to monitors
140 dcache = dcache_mon
141
116
117 if options.memchecker:
118 system.memchecker = MemChecker()
119
120 for i in range(options.num_cpus):
121 if options.caches:
122 icache = icache_class(size=options.l1i_size,
123 assoc=options.l1i_assoc)

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143 dcache_mon.memchecker = system.memchecker
144
145 # Connect monitor
146 dcache_mon.mem_side = dcache.cpu_side
147
148 # Let CPU connect to monitors
149 dcache = dcache_mon
150
151 if options.l1d_hwp_type:
152 hwpClass = HWPConfig.get(options.l1d_hwp_type)
153 if dcache.prefetcher != m5.params.NULL:
154 print("Warning: l1d-hwp-type is set (", hwpClass, "), but",
155 "the current l1d has a default Hardware Prefetcher",
156 "of type", type(dcache.prefetcher), ", using the",
157 "specified by the flag option.")
158 dcache.prefetcher = hwpClass()
159
160 if options.l1i_hwp_type:
161 hwpClass = HWPConfig.get(options.l1i_hwp_type)
162 if icache.prefetcher != m5.params.NULL:
163 print("Warning: l1i-hwp-type is set (", hwpClass, "), but",
164 "the current l1i has a default Hardware Prefetcher",
165 "of type", type(icache.prefetcher), ", using the",
166 "specified by the flag option.")
167 icache.prefetcher = hwpClass()
168
142 # When connecting the caches, the clock is also inherited
143 # from the CPU in question
144 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
145 iwalkcache, dwalkcache)
146
147 if options.memchecker:
148 # The mem_side ports of the caches haven't been connected yet.
149 # Make sure connectAllPorts connects the right objects.

--- 50 unchanged lines hidden --- 		169 # When connecting the caches, the clock is also inherited
170 # from the CPU in question
171 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
172 iwalkcache, dwalkcache)
173
174 if options.memchecker:
175 # The mem_side ports of the caches haven't been connected yet.
176 # Make sure connectAllPorts connects the right objects.

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