CacheConfig.py (13806:e2ca4f169e82) CacheConfig.py (13811:88827de8fced)
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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62 except:
63 print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
64 sys.exit(1)
65
66 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
67 core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
68 core.O3_ARM_v7aL2, \
69 core.O3_ARM_v7aWalkCache
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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62 except:
63 print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
64 sys.exit(1)
65
66 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
67 core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
68 core.O3_ARM_v7aL2, \
69 core.O3_ARM_v7aWalkCache
70 elif options.cpu_type == "HPI":
71 try:
72 import cores.arm.HPI as core
73 except:
74 print("HPI is unavailable.")
75 sys.exit(1)
76
77 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
78 core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache
70 else:
71 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
72 L1_DCache, L1_ICache, L2Cache, None
73
74 if buildEnv['TARGET_ISA'] == 'x86':
75 walk_cache_class = PageTableWalkerCache
76
77 # Set the cache line size of the system

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80 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
81 L1_DCache, L1_ICache, L2Cache, None
82
83 if buildEnv['TARGET_ISA'] == 'x86':
84 walk_cache_class = PageTableWalkerCache
85
86 # Set the cache line size of the system

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