CacheConfig.py (11501:9345c4320477) | CacheConfig.py (11539:de57dbf319d0) |
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1# Copyright (c) 2012-2013, 2015 ARM Limited | 1# Copyright (c) 2012-2013, 2015-2016 ARM Limited |
2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 45 unchanged lines hidden (view full) --- 55 56 if options.cpu_type == "arm_detailed": 57 try: 58 from O3_ARM_v7a import * 59 except: 60 print "arm_detailed is unavailable. Did you compile the O3 model?" 61 sys.exit(1) 62 | 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 45 unchanged lines hidden (view full) --- 55 56 if options.cpu_type == "arm_detailed": 57 try: 58 from O3_ARM_v7a import * 59 except: 60 print "arm_detailed is unavailable. Did you compile the O3 model?" 61 sys.exit(1) 62 |
63 dcache_class, icache_class, l2_cache_class = \ 64 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 | 63 dcache_class, icache_class, l2_cache_class, walk_cache_class = \ 64 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \ 65 O3_ARM_v7aWalkCache |
65 else: | 66 else: |
66 dcache_class, icache_class, l2_cache_class = \ 67 L1_DCache, L1_ICache, L2Cache | 67 dcache_class, icache_class, l2_cache_class, walk_cache_class = \ 68 L1_DCache, L1_ICache, L2Cache, None |
68 | 69 |
70 if buildEnv['TARGET_ISA'] == 'x86': 71 walk_cache_class = PageTableWalkerCache 72 |
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69 # Set the cache line size of the system 70 system.cache_line_size = options.cacheline_size 71 72 # If elastic trace generation is enabled, make sure the memory system is 73 # minimal so that compute delays do not include memory access latencies. 74 # Configure the compulsory L1 caches for the O3CPU, do not configure 75 # any more caches. 76 if options.l2cache and options.elastic_trace_en: --- 16 unchanged lines hidden (view full) --- 93 94 for i in xrange(options.num_cpus): 95 if options.caches: 96 icache = icache_class(size=options.l1i_size, 97 assoc=options.l1i_assoc) 98 dcache = dcache_class(size=options.l1d_size, 99 assoc=options.l1d_assoc) 100 | 73 # Set the cache line size of the system 74 system.cache_line_size = options.cacheline_size 75 76 # If elastic trace generation is enabled, make sure the memory system is 77 # minimal so that compute delays do not include memory access latencies. 78 # Configure the compulsory L1 caches for the O3CPU, do not configure 79 # any more caches. 80 if options.l2cache and options.elastic_trace_en: --- 16 unchanged lines hidden (view full) --- 97 98 for i in xrange(options.num_cpus): 99 if options.caches: 100 icache = icache_class(size=options.l1i_size, 101 assoc=options.l1i_assoc) 102 dcache = dcache_class(size=options.l1d_size, 103 assoc=options.l1d_assoc) 104 |
105 # If we have a walker cache specified, instantiate two 106 # instances here 107 if walk_cache_class: 108 iwalkcache = walk_cache_class() 109 dwalkcache = walk_cache_class() 110 else: 111 iwalkcache = None 112 dwalkcache = None 113 |
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101 if options.memchecker: 102 dcache_mon = MemCheckerMonitor(warn_only=True) 103 dcache_real = dcache 104 105 # Do not pass the memchecker into the constructor of 106 # MemCheckerMonitor, as it would create a copy; we require 107 # exactly one MemChecker instance. 108 dcache_mon.memchecker = system.memchecker 109 110 # Connect monitor 111 dcache_mon.mem_side = dcache.cpu_side 112 113 # Let CPU connect to monitors 114 dcache = dcache_mon 115 116 # When connecting the caches, the clock is also inherited 117 # from the CPU in question | 114 if options.memchecker: 115 dcache_mon = MemCheckerMonitor(warn_only=True) 116 dcache_real = dcache 117 118 # Do not pass the memchecker into the constructor of 119 # MemCheckerMonitor, as it would create a copy; we require 120 # exactly one MemChecker instance. 121 dcache_mon.memchecker = system.memchecker 122 123 # Connect monitor 124 dcache_mon.mem_side = dcache.cpu_side 125 126 # Let CPU connect to monitors 127 dcache = dcache_mon 128 129 # When connecting the caches, the clock is also inherited 130 # from the CPU in question |
118 if buildEnv['TARGET_ISA'] == 'x86': 119 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 120 PageTableWalkerCache(), 121 PageTableWalkerCache()) 122 else: 123 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) | 131 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 132 iwalkcache, dwalkcache) |
124 125 if options.memchecker: 126 # The mem_side ports of the caches haven't been connected yet. 127 # Make sure connectAllPorts connects the right objects. 128 system.cpu[i].dcache = dcache_real 129 system.cpu[i].dcache_mon = dcache_mon 130 131 elif options.external_memory_system: --- 51 unchanged lines hidden --- | 133 134 if options.memchecker: 135 # The mem_side ports of the caches haven't been connected yet. 136 # Make sure connectAllPorts connects the right objects. 137 system.cpu[i].dcache = dcache_real 138 system.cpu[i].dcache_mon = dcache_mon 139 140 elif options.external_memory_system: --- 51 unchanged lines hidden --- |