CacheConfig.py (11320:42ecb523c64a) CacheConfig.py (11501:9345c4320477)
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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148 system.cpu[i].createInterruptController()
149 if options.l2cache:
150 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
151 elif options.external_memory_system:
152 system.cpu[i].connectUncachedPorts(system.membus)
153 else:
154 system.cpu[i].connectAllPorts(system.membus)
155
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 139 unchanged lines hidden (view full) ---

148 system.cpu[i].createInterruptController()
149 if options.l2cache:
150 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
151 elif options.external_memory_system:
152 system.cpu[i].connectUncachedPorts(system.membus)
153 else:
154 system.cpu[i].connectAllPorts(system.membus)
155
156 # Add a snoop filter to the membus if there are caches above it
157 if (options.l2cache or options.caches) and \
158 (system.membus.snoop_filter == NULL):
159 system.membus.snoop_filter = SnoopFilter()
160
156 return system
157
158# ExternalSlave provides a "port", but when that port connects to a cache,
159# the connecting CPU SimObject wants to refer to its "cpu_side".
160# The 'ExternalCache' class provides this adaptation by rewriting the name,
161# eliminating distracting changes elsewhere in the config code.
162class ExternalCache(ExternalSlave):
163 def __getattr__(cls, attr):

--- 14 unchanged lines hidden --- 		161 return system
162
163# ExternalSlave provides a "port", but when that port connects to a cache,
164# the connecting CPU SimObject wants to refer to its "cpu_side".
165# The 'ExternalCache' class provides this adaptation by rewriting the name,
166# eliminating distracting changes elsewhere in the config code.
167class ExternalCache(ExternalSlave):
168 def __getattr__(cls, attr):

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