CacheConfig.py (10613:9d0aef7a9b2e) CacheConfig.py (10720:67b3e74de9ae)
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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60 L1Cache, L1Cache, L2Cache
61
62 # Set the cache line size of the system
63 system.cache_line_size = options.cacheline_size
64
65 if options.l2cache:
66 # Provide a clock for the L2 and the L1-to-L2 bus here as they
67 # are not connected using addTwoLevelCacheHierarchy. Use the
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 51 unchanged lines hidden (view full) ---

60 L1Cache, L1Cache, L2Cache
61
62 # Set the cache line size of the system
63 system.cache_line_size = options.cacheline_size
64
65 if options.l2cache:
66 # Provide a clock for the L2 and the L1-to-L2 bus here as they
67 # are not connected using addTwoLevelCacheHierarchy. Use the
68 # same clock as the CPUs, and set the L1-to-L2 bus width to 32
69 # bytes (256 bits).
68 # same clock as the CPUs.
70 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
71 size=options.l2_size,
72 assoc=options.l2_assoc)
73
69 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
70 size=options.l2_size,
71 assoc=options.l2_assoc)
72
74 system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
75 width = 32)
73 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
76 system.l2.cpu_side = system.tol2bus.master
77 system.l2.mem_side = system.membus.slave
78
79 if options.memchecker:
80 system.memchecker = MemChecker()
81
82 for i in xrange(options.num_cpus):
83 if options.caches:

--- 42 unchanged lines hidden --- 		74 system.l2.cpu_side = system.tol2bus.master
75 system.l2.mem_side = system.membus.slave
76
77 if options.memchecker:
78 system.memchecker = MemChecker()
79
80 for i in xrange(options.num_cpus):
81 if options.caches:

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