CacheConfig.py (10405:7a618c07e663) | CacheConfig.py (10613:9d0aef7a9b2e) |
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1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 62 unchanged lines hidden (view full) --- 71 size=options.l2_size, 72 assoc=options.l2_assoc) 73 74 system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain, 75 width = 32) 76 system.l2.cpu_side = system.tol2bus.master 77 system.l2.mem_side = system.membus.slave 78 | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 62 unchanged lines hidden (view full) --- 71 size=options.l2_size, 72 assoc=options.l2_assoc) 73 74 system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain, 75 width = 32) 76 system.l2.cpu_side = system.tol2bus.master 77 system.l2.mem_side = system.membus.slave 78 |
79 if options.memchecker: 80 system.memchecker = MemChecker() 81 |
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79 for i in xrange(options.num_cpus): 80 if options.caches: 81 icache = icache_class(size=options.l1i_size, 82 assoc=options.l1i_assoc) 83 dcache = dcache_class(size=options.l1d_size, 84 assoc=options.l1d_assoc) 85 | 82 for i in xrange(options.num_cpus): 83 if options.caches: 84 icache = icache_class(size=options.l1i_size, 85 assoc=options.l1i_assoc) 86 dcache = dcache_class(size=options.l1d_size, 87 assoc=options.l1d_assoc) 88 |
89 if options.memchecker: 90 dcache_mon = MemCheckerMonitor(warn_only=True) 91 dcache_real = dcache 92 93 # Do not pass the memchecker into the constructor of 94 # MemCheckerMonitor, as it would create a copy; we require 95 # exactly one MemChecker instance. 96 dcache_mon.memchecker = system.memchecker 97 98 # Connect monitor 99 dcache_mon.mem_side = dcache.cpu_side 100 101 # Let CPU connect to monitors 102 dcache = dcache_mon 103 |
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86 # When connecting the caches, the clock is also inherited 87 # from the CPU in question 88 if buildEnv['TARGET_ISA'] == 'x86': 89 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 90 PageTableWalkerCache(), 91 PageTableWalkerCache()) 92 else: 93 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) | 104 # When connecting the caches, the clock is also inherited 105 # from the CPU in question 106 if buildEnv['TARGET_ISA'] == 'x86': 107 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 108 PageTableWalkerCache(), 109 PageTableWalkerCache()) 110 else: 111 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) |
112 113 if options.memchecker: 114 # The mem_side ports of the caches haven't been connected yet. 115 # Make sure connectAllPorts connects the right objects. 116 system.cpu[i].dcache = dcache_real 117 system.cpu[i].dcache_mon = dcache_mon 118 |
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94 system.cpu[i].createInterruptController() 95 if options.l2cache: 96 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 97 else: 98 system.cpu[i].connectAllPorts(system.membus) 99 100 return system | 119 system.cpu[i].createInterruptController() 120 if options.l2cache: 121 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 122 else: 123 system.cpu[i].connectAllPorts(system.membus) 124 125 return system |