1# Copyright (c) 2010 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 29 unchanged lines hidden (view full) --- 38 system.l2 = L2Cache(size='2MB') 39 system.tol2bus = Bus() 40 system.l2.cpu_side = system.tol2bus.port 41 system.l2.mem_side = system.membus.port 42 system.l2.num_cpus = options.num_cpus 43 44 for i in xrange(options.num_cpus): 45 if options.caches: |
46 if buildEnv['TARGET_ISA'] == 'x86': 47 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 48 L1Cache(size = '64kB'), 49 PageTableWalkerCache(), 50 PageTableWalkerCache()) 51 else: 52 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 53 L1Cache(size = '64kB')) |
54 if options.l2cache: 55 system.cpu[i].connectMemPorts(system.tol2bus) 56 else: 57 system.cpu[i].connectMemPorts(system.membus) 58 59 return system |