1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44from __future__ import print_function
45
46import m5
47from m5.objects import *
48from Caches import *
49
50def config_cache(options, system):
51 if options.external_memory_system and (options.caches or options.l2cache):
50 print "External caches and internal caches are exclusive options.\n"
52 print("External caches and internal caches are exclusive options.\n")
53 sys.exit(1)
54
55 if options.external_memory_system:
56 ExternalCache = ExternalCacheFactory(options.external_memory_system)
57
58 if options.cpu_type == "O3_ARM_v7a_3":
59 try:
60 from cores.arm.O3_ARM_v7a import *
61 except:
60 print "O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?"
62 print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
63 sys.exit(1)
64
65 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
66 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
67 O3_ARM_v7aWalkCache
68 else:
69 dcache_class, icache_class, l2_cache_class, walk_cache_class = \
70 L1_DCache, L1_ICache, L2Cache, None

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