1c1
< # Copyright (c) 2012 ARM Limited
---
> # Copyright (c) 2012-2013 ARM Limited
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< system.l2 = l2_cache_class(clock=options.cpu_clock,
---
> system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
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< system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32)
---
> system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
> width = 32)