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> # Provide a clock for the L2 and the L1-to-L2 bus here as they
> # are not connected using addTwoLevelCacheHierarchy. Use the
> # same clock as the CPUs, and set the L1-to-L2 bus width to 32
> # bytes (256 bits).
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< system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
< block_size=options.cacheline_size)
---
> system.l2 = O3_ARM_v7aL2(clock = options.clock,
> size = options.l2_size,
> assoc = options.l2_assoc,
> block_size=options.cacheline_size)
43,44c49,52
< system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
< block_size=options.cacheline_size)
---
> system.l2 = L2Cache(clock = options.clock,
> size = options.l2_size,
> assoc = options.l2_assoc,
> block_size = options.cacheline_size)
46c54
< system.tol2bus = CoherentBus()
---
> system.tol2bus = CoherentBus(clock = options.clock, width = 32)
54,55c62,63
< assoc = options.l1i_assoc,
< block_size=options.cacheline_size)
---
> assoc = options.l1i_assoc,
> block_size=options.cacheline_size)
57,58c65,66
< assoc = options.l1d_assoc,
< block_size=options.cacheline_size)
---
> assoc = options.l1d_assoc,
> block_size=options.cacheline_size)
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> # When connecting the caches, the clock is also inherited
> # from the CPU in question