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< # Copyright (c) 2012-2013, 2015 ARM Limited
---
> # Copyright (c) 2012-2013, 2015-2016 ARM Limited
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< dcache_class, icache_class, l2_cache_class = \
< O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
---
> dcache_class, icache_class, l2_cache_class, walk_cache_class = \
> O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
> O3_ARM_v7aWalkCache
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< dcache_class, icache_class, l2_cache_class = \
< L1_DCache, L1_ICache, L2Cache
---
> dcache_class, icache_class, l2_cache_class, walk_cache_class = \
> L1_DCache, L1_ICache, L2Cache, None
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> if buildEnv['TARGET_ISA'] == 'x86':
> walk_cache_class = PageTableWalkerCache
>
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> # If we have a walker cache specified, instantiate two
> # instances here
> if walk_cache_class:
> iwalkcache = walk_cache_class()
> dwalkcache = walk_cache_class()
> else:
> iwalkcache = None
> dwalkcache = None
>
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< if buildEnv['TARGET_ISA'] == 'x86':
< system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
< PageTableWalkerCache(),
< PageTableWalkerCache())
< else:
< system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
---
> system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
> iwalkcache, dwalkcache)