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< # Copyright (c) 2012-2013 ARM Limited
---
> # Copyright (c) 2012-2013, 2015 ARM Limited
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> if options.external_memory_system and (options.caches or options.l2cache):
> print "External caches and internal caches are exclusive options.\n"
> sys.exit(1)
>
> if options.external_memory_system:
> ExternalCache = ExternalCacheFactory(options.external_memory_system)
>
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> elif options.external_memory_system:
> # These port names are presented to whatever 'external' system
> # gem5 is connecting to. Its configuration will likely depend
> # on these names. For simplicity, we would advise configuring
> # it to use this naming scheme; if this isn't possible, change
> # the names below.
> if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
> system.cpu[i].addPrivateSplitL1Caches(
> ExternalCache("cpu%d.icache" % i),
> ExternalCache("cpu%d.dcache" % i),
> ExternalCache("cpu%d.itb_walker_cache" % i),
> ExternalCache("cpu%d.dtb_walker_cache" % i))
> else:
> system.cpu[i].addPrivateSplitL1Caches(
> ExternalCache("cpu%d.icache" % i),
> ExternalCache("cpu%d.dcache" % i))
>
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> elif options.external_memory_system:
> system.cpu[i].connectUncachedPorts(system.membus)
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>
> # ExternalSlave provides a "port", but when that port connects to a cache,
> # the connecting CPU SimObject wants to refer to its "cpu_side".
> # The 'ExternalCache' class provides this adaptation by rewriting the name,
> # eliminating distracting changes elsewhere in the config code.
> class ExternalCache(ExternalSlave):
> def __getattr__(cls, attr):
> if (attr == "cpu_side"):
> attr = "port"
> return super(ExternalSlave, cls).__getattr__(attr)
>
> def __setattr__(cls, attr, value):
> if (attr == "cpu_side"):
> attr = "port"
> return super(ExternalSlave, cls).__setattr__(attr, value)
>
> def ExternalCacheFactory(port_type):
> def make(name):
> return ExternalCache(port_data=name, port_type=port_type,
> addr_ranges=[AllMemory])
> return make