68,69c68
< # same clock as the CPUs, and set the L1-to-L2 bus width to 32
< # bytes (256 bits).
---
> # same clock as the CPUs.
74,75c73
< system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
< width = 32)
---
> system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)