1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35
36def config_cache(options, system):
37 if options.l2cache:
38 system.l2 = L2Cache(size='2MB')
39 system.tol2bus = Bus()
40 system.l2.cpu_side = system.tol2bus.port
41 system.l2.mem_side = system.membus.port
42 system.l2.num_cpus = options.num_cpus
43
44 for i in xrange(options.num_cpus):
45 if options.caches:
46 if buildEnv['TARGET_ISA'] == 'x86':
47 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
48 L1Cache(size = '64kB'),
49 PageTableWalkerCache(),
50 PageTableWalkerCache())
51 else:
52 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
53 L1Cache(size = '64kB'))
54 if options.l2cache:
| 1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35
36def config_cache(options, system):
37 if options.l2cache:
38 system.l2 = L2Cache(size='2MB')
39 system.tol2bus = Bus()
40 system.l2.cpu_side = system.tol2bus.port
41 system.l2.mem_side = system.membus.port
42 system.l2.num_cpus = options.num_cpus
43
44 for i in xrange(options.num_cpus):
45 if options.caches:
46 if buildEnv['TARGET_ISA'] == 'x86':
47 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
48 L1Cache(size = '64kB'),
49 PageTableWalkerCache(),
50 PageTableWalkerCache())
51 else:
52 system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
53 L1Cache(size = '64kB'))
54 if options.l2cache:
|