1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010 Advanced Micro Devices, Inc.
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44import m5
45from m5.objects import *
46from Caches import *
47
48def config_cache(options, system):
49 if options.external_memory_system and (options.caches or options.l2cache):
50 print "External caches and internal caches are exclusive options.\n"
51 sys.exit(1)
52
53 if options.external_memory_system:
54 ExternalCache = ExternalCacheFactory(options.external_memory_system)
55
56 if options.cpu_type == "arm_detailed":
57 try:
58 from O3_ARM_v7a import *
59 except:
60 print "arm_detailed is unavailable. Did you compile the O3 model?"
61 sys.exit(1)
62
63 dcache_class, icache_class, l2_cache_class = \
64 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
65 else:
66 dcache_class, icache_class, l2_cache_class = \
67 L1_DCache, L1_ICache, L2Cache
68
69 # Set the cache line size of the system
70 system.cache_line_size = options.cacheline_size
71
| 1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010 Advanced Micro Devices, Inc.
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Lisa Hsu
40
41# Configure the M5 cache hierarchy config in one place
42#
43
44import m5
45from m5.objects import *
46from Caches import *
47
48def config_cache(options, system):
49 if options.external_memory_system and (options.caches or options.l2cache):
50 print "External caches and internal caches are exclusive options.\n"
51 sys.exit(1)
52
53 if options.external_memory_system:
54 ExternalCache = ExternalCacheFactory(options.external_memory_system)
55
56 if options.cpu_type == "arm_detailed":
57 try:
58 from O3_ARM_v7a import *
59 except:
60 print "arm_detailed is unavailable. Did you compile the O3 model?"
61 sys.exit(1)
62
63 dcache_class, icache_class, l2_cache_class = \
64 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
65 else:
66 dcache_class, icache_class, l2_cache_class = \
67 L1_DCache, L1_ICache, L2Cache
68
69 # Set the cache line size of the system
70 system.cache_line_size = options.cacheline_size
71
|
72 if options.l2cache:
73 # Provide a clock for the L2 and the L1-to-L2 bus here as they
74 # are not connected using addTwoLevelCacheHierarchy. Use the
75 # same clock as the CPUs.
76 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
77 size=options.l2_size,
78 assoc=options.l2_assoc)
79
80 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
81 system.l2.cpu_side = system.tol2bus.master
82 system.l2.mem_side = system.membus.slave
83
84 if options.memchecker:
85 system.memchecker = MemChecker()
86
87 for i in xrange(options.num_cpus):
88 if options.caches:
89 icache = icache_class(size=options.l1i_size,
90 assoc=options.l1i_assoc)
91 dcache = dcache_class(size=options.l1d_size,
92 assoc=options.l1d_assoc)
93
94 if options.memchecker:
95 dcache_mon = MemCheckerMonitor(warn_only=True)
96 dcache_real = dcache
97
98 # Do not pass the memchecker into the constructor of
99 # MemCheckerMonitor, as it would create a copy; we require
100 # exactly one MemChecker instance.
101 dcache_mon.memchecker = system.memchecker
102
103 # Connect monitor
104 dcache_mon.mem_side = dcache.cpu_side
105
106 # Let CPU connect to monitors
107 dcache = dcache_mon
108
109 # When connecting the caches, the clock is also inherited
110 # from the CPU in question
111 if buildEnv['TARGET_ISA'] == 'x86':
112 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
113 PageTableWalkerCache(),
114 PageTableWalkerCache())
115 else:
116 system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
117
118 if options.memchecker:
119 # The mem_side ports of the caches haven't been connected yet.
120 # Make sure connectAllPorts connects the right objects.
121 system.cpu[i].dcache = dcache_real
122 system.cpu[i].dcache_mon = dcache_mon
123
124 elif options.external_memory_system:
125 # These port names are presented to whatever 'external' system
126 # gem5 is connecting to. Its configuration will likely depend
127 # on these names. For simplicity, we would advise configuring
128 # it to use this naming scheme; if this isn't possible, change
129 # the names below.
130 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
131 system.cpu[i].addPrivateSplitL1Caches(
132 ExternalCache("cpu%d.icache" % i),
133 ExternalCache("cpu%d.dcache" % i),
134 ExternalCache("cpu%d.itb_walker_cache" % i),
135 ExternalCache("cpu%d.dtb_walker_cache" % i))
136 else:
137 system.cpu[i].addPrivateSplitL1Caches(
138 ExternalCache("cpu%d.icache" % i),
139 ExternalCache("cpu%d.dcache" % i))
140
141 system.cpu[i].createInterruptController()
142 if options.l2cache:
143 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
144 elif options.external_memory_system:
145 system.cpu[i].connectUncachedPorts(system.membus)
146 else:
147 system.cpu[i].connectAllPorts(system.membus)
148
149 return system
150
151# ExternalSlave provides a "port", but when that port connects to a cache,
152# the connecting CPU SimObject wants to refer to its "cpu_side".
153# The 'ExternalCache' class provides this adaptation by rewriting the name,
154# eliminating distracting changes elsewhere in the config code.
155class ExternalCache(ExternalSlave):
156 def __getattr__(cls, attr):
157 if (attr == "cpu_side"):
158 attr = "port"
159 return super(ExternalSlave, cls).__getattr__(attr)
160
161 def __setattr__(cls, attr, value):
162 if (attr == "cpu_side"):
163 attr = "port"
164 return super(ExternalSlave, cls).__setattr__(attr, value)
165
166def ExternalCacheFactory(port_type):
167 def make(name):
168 return ExternalCache(port_data=name, port_type=port_type,
169 addr_ranges=[AllMemory])
170 return make
| 79 if options.l2cache:
80 # Provide a clock for the L2 and the L1-to-L2 bus here as they
81 # are not connected using addTwoLevelCacheHierarchy. Use the
82 # same clock as the CPUs.
83 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
84 size=options.l2_size,
85 assoc=options.l2_assoc)
86
87 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
88 system.l2.cpu_side = system.tol2bus.master
89 system.l2.mem_side = system.membus.slave
90
91 if options.memchecker:
92 system.memchecker = MemChecker()
93
94 for i in xrange(options.num_cpus):
95 if options.caches:
96 icache = icache_class(size=options.l1i_size,
97 assoc=options.l1i_assoc)
98 dcache = dcache_class(size=options.l1d_size,
99 assoc=options.l1d_assoc)
100
101 if options.memchecker:
102 dcache_mon = MemCheckerMonitor(warn_only=True)
103 dcache_real = dcache
104
105 # Do not pass the memchecker into the constructor of
106 # MemCheckerMonitor, as it would create a copy; we require
107 # exactly one MemChecker instance.
108 dcache_mon.memchecker = system.memchecker
109
110 # Connect monitor
111 dcache_mon.mem_side = dcache.cpu_side
112
113 # Let CPU connect to monitors
114 dcache = dcache_mon
115
116 # When connecting the caches, the clock is also inherited
117 # from the CPU in question
118 if buildEnv['TARGET_ISA'] == 'x86':
119 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
120 PageTableWalkerCache(),
121 PageTableWalkerCache())
122 else:
123 system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
124
125 if options.memchecker:
126 # The mem_side ports of the caches haven't been connected yet.
127 # Make sure connectAllPorts connects the right objects.
128 system.cpu[i].dcache = dcache_real
129 system.cpu[i].dcache_mon = dcache_mon
130
131 elif options.external_memory_system:
132 # These port names are presented to whatever 'external' system
133 # gem5 is connecting to. Its configuration will likely depend
134 # on these names. For simplicity, we would advise configuring
135 # it to use this naming scheme; if this isn't possible, change
136 # the names below.
137 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
138 system.cpu[i].addPrivateSplitL1Caches(
139 ExternalCache("cpu%d.icache" % i),
140 ExternalCache("cpu%d.dcache" % i),
141 ExternalCache("cpu%d.itb_walker_cache" % i),
142 ExternalCache("cpu%d.dtb_walker_cache" % i))
143 else:
144 system.cpu[i].addPrivateSplitL1Caches(
145 ExternalCache("cpu%d.icache" % i),
146 ExternalCache("cpu%d.dcache" % i))
147
148 system.cpu[i].createInterruptController()
149 if options.l2cache:
150 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
151 elif options.external_memory_system:
152 system.cpu[i].connectUncachedPorts(system.membus)
153 else:
154 system.cpu[i].connectAllPorts(system.membus)
155
156 return system
157
158# ExternalSlave provides a "port", but when that port connects to a cache,
159# the connecting CPU SimObject wants to refer to its "cpu_side".
160# The 'ExternalCache' class provides this adaptation by rewriting the name,
161# eliminating distracting changes elsewhere in the config code.
162class ExternalCache(ExternalSlave):
163 def __getattr__(cls, attr):
164 if (attr == "cpu_side"):
165 attr = "port"
166 return super(ExternalSlave, cls).__getattr__(attr)
167
168 def __setattr__(cls, attr, value):
169 if (attr == "cpu_side"):
170 attr = "port"
171 return super(ExternalSlave, cls).__setattr__(attr, value)
172
173def ExternalCacheFactory(port_type):
174 def make(name):
175 return ExternalCache(port_data=name, port_type=port_type,
176 addr_ranges=[AllMemory])
177 return make
|