CacheConfig.py (9793:6e6cefc1db1f) | CacheConfig.py (9815:3b3b94536547) |
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1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 45 unchanged lines hidden (view full) --- 54 sys.exit(1) 55 56 dcache_class, icache_class, l2_cache_class = \ 57 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 58 else: 59 dcache_class, icache_class, l2_cache_class = \ 60 L1Cache, L1Cache, L2Cache 61 | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 45 unchanged lines hidden (view full) --- 54 sys.exit(1) 55 56 dcache_class, icache_class, l2_cache_class = \ 57 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 58 else: 59 dcache_class, icache_class, l2_cache_class = \ 60 L1Cache, L1Cache, L2Cache 61 |
62 # Set the cache line size of the system 63 system.cache_line_size = options.cacheline_size 64 |
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62 if options.l2cache: 63 # Provide a clock for the L2 and the L1-to-L2 bus here as they 64 # are not connected using addTwoLevelCacheHierarchy. Use the 65 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 66 # bytes (256 bits). 67 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 68 size=options.l2_size, | 65 if options.l2cache: 66 # Provide a clock for the L2 and the L1-to-L2 bus here as they 67 # are not connected using addTwoLevelCacheHierarchy. Use the 68 # same clock as the CPUs, and set the L1-to-L2 bus width to 32 69 # bytes (256 bits). 70 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, 71 size=options.l2_size, |
69 assoc=options.l2_assoc, 70 block_size=options.cacheline_size) | 72 assoc=options.l2_assoc) |
71 72 system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, 73 width = 32) 74 system.l2.cpu_side = system.tol2bus.master 75 system.l2.mem_side = system.membus.slave 76 77 for i in xrange(options.num_cpus): 78 if options.caches: 79 icache = icache_class(size=options.l1i_size, | 73 74 system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, 75 width = 32) 76 system.l2.cpu_side = system.tol2bus.master 77 system.l2.mem_side = system.membus.slave 78 79 for i in xrange(options.num_cpus): 80 if options.caches: 81 icache = icache_class(size=options.l1i_size, |
80 assoc=options.l1i_assoc, 81 block_size=options.cacheline_size) | 82 assoc=options.l1i_assoc) |
82 dcache = dcache_class(size=options.l1d_size, | 83 dcache = dcache_class(size=options.l1d_size, |
83 assoc=options.l1d_assoc, 84 block_size=options.cacheline_size) | 84 assoc=options.l1d_assoc) |
85 86 # When connecting the caches, the clock is also inherited 87 # from the CPU in question 88 if buildEnv['TARGET_ISA'] == 'x86': 89 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 90 PageTableWalkerCache(), 91 PageTableWalkerCache()) 92 else: 93 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 94 system.cpu[i].createInterruptController() 95 if options.l2cache: 96 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 97 else: 98 system.cpu[i].connectAllPorts(system.membus) 99 100 return system | 85 86 # When connecting the caches, the clock is also inherited 87 # from the CPU in question 88 if buildEnv['TARGET_ISA'] == 'x86': 89 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 90 PageTableWalkerCache(), 91 PageTableWalkerCache()) 92 else: 93 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 94 system.cpu[i].createInterruptController() 95 if options.l2cache: 96 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) 97 else: 98 system.cpu[i].connectAllPorts(system.membus) 99 100 return system |