CacheConfig.py (10720:67b3e74de9ae) | CacheConfig.py (10780:46070443051e) |
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1# Copyright (c) 2012-2013 ARM Limited | 1# Copyright (c) 2012-2013, 2015 ARM Limited |
2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 31 unchanged lines hidden (view full) --- 41# Configure the M5 cache hierarchy config in one place 42# 43 44import m5 45from m5.objects import * 46from Caches import * 47 48def config_cache(options, system): | 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 31 unchanged lines hidden (view full) --- 41# Configure the M5 cache hierarchy config in one place 42# 43 44import m5 45from m5.objects import * 46from Caches import * 47 48def config_cache(options, system): |
49 if options.external_memory_system and (options.caches or options.l2cache): 50 print "External caches and internal caches are exclusive options.\n" 51 sys.exit(1) 52 53 if options.external_memory_system: 54 ExternalCache = ExternalCacheFactory(options.external_memory_system) 55 |
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49 if options.cpu_type == "arm_detailed": 50 try: 51 from O3_ARM_v7a import * 52 except: 53 print "arm_detailed is unavailable. Did you compile the O3 model?" 54 sys.exit(1) 55 56 dcache_class, icache_class, l2_cache_class = \ --- 52 unchanged lines hidden (view full) --- 109 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 110 111 if options.memchecker: 112 # The mem_side ports of the caches haven't been connected yet. 113 # Make sure connectAllPorts connects the right objects. 114 system.cpu[i].dcache = dcache_real 115 system.cpu[i].dcache_mon = dcache_mon 116 | 56 if options.cpu_type == "arm_detailed": 57 try: 58 from O3_ARM_v7a import * 59 except: 60 print "arm_detailed is unavailable. Did you compile the O3 model?" 61 sys.exit(1) 62 63 dcache_class, icache_class, l2_cache_class = \ --- 52 unchanged lines hidden (view full) --- 116 system.cpu[i].addPrivateSplitL1Caches(icache, dcache) 117 118 if options.memchecker: 119 # The mem_side ports of the caches haven't been connected yet. 120 # Make sure connectAllPorts connects the right objects. 121 system.cpu[i].dcache = dcache_real 122 system.cpu[i].dcache_mon = dcache_mon 123 |
124 elif options.external_memory_system: 125 # These port names are presented to whatever 'external' system 126 # gem5 is connecting to. Its configuration will likely depend 127 # on these names. For simplicity, we would advise configuring 128 # it to use this naming scheme; if this isn't possible, change 129 # the names below. 130 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 131 system.cpu[i].addPrivateSplitL1Caches( 132 ExternalCache("cpu%d.icache" % i), 133 ExternalCache("cpu%d.dcache" % i), 134 ExternalCache("cpu%d.itb_walker_cache" % i), 135 ExternalCache("cpu%d.dtb_walker_cache" % i)) 136 else: 137 system.cpu[i].addPrivateSplitL1Caches( 138 ExternalCache("cpu%d.icache" % i), 139 ExternalCache("cpu%d.dcache" % i)) 140 |
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117 system.cpu[i].createInterruptController() 118 if options.l2cache: 119 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) | 141 system.cpu[i].createInterruptController() 142 if options.l2cache: 143 system.cpu[i].connectAllPorts(system.tol2bus, system.membus) |
144 elif options.external_memory_system: 145 system.cpu[i].connectUncachedPorts(system.membus) |
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120 else: 121 system.cpu[i].connectAllPorts(system.membus) 122 123 return system | 146 else: 147 system.cpu[i].connectAllPorts(system.membus) 148 149 return system |
150 151# ExternalSlave provides a "port", but when that port connects to a cache, 152# the connecting CPU SimObject wants to refer to its "cpu_side". 153# The 'ExternalCache' class provides this adaptation by rewriting the name, 154# eliminating distracting changes elsewhere in the config code. 155class ExternalCache(ExternalSlave): 156 def __getattr__(cls, attr): 157 if (attr == "cpu_side"): 158 attr = "port" 159 return super(ExternalSlave, cls).__getattr__(attr) 160 161 def __setattr__(cls, attr, value): 162 if (attr == "cpu_side"): 163 attr = "port" 164 return super(ExternalSlave, cls).__setattr__(attr, value) 165 166def ExternalCacheFactory(port_type): 167 def make(name): 168 return ExternalCache(port_data=name, port_type=port_type, 169 addr_ranges=[AllMemory]) 170 return make |
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