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1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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64 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
65 else:
66 dcache_class, icache_class, l2_cache_class = \
67 L1_DCache, L1_ICache, L2Cache
68
69 # Set the cache line size of the system
70 system.cache_line_size = options.cacheline_size
71
72 if options.l2cache:
73 # Provide a clock for the L2 and the L1-to-L2 bus here as they
74 # are not connected using addTwoLevelCacheHierarchy. Use the
75 # same clock as the CPUs.
76 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
77 size=options.l2_size,
78 assoc=options.l2_assoc)
79

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