1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 31 unchanged lines hidden (view full) ---

41# Configure the M5 cache hierarchy config in one place
42#
43
44import m5
45from m5.objects import *
46from Caches import *
47
48def config_cache(options, system):
49 if options.cpu_type == "arm_detailed":
50 try:
51 from O3_ARM_v7a import *
52 except:
53 print "arm_detailed is unavailable. Did you compile the O3 model?"
54 sys.exit(1)
55
56 dcache_class, icache_class, l2_cache_class = \

--- 52 unchanged lines hidden (view full) ---

109 system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
110
111 if options.memchecker:
112 # The mem_side ports of the caches haven't been connected yet.
113 # Make sure connectAllPorts connects the right objects.
114 system.cpu[i].dcache = dcache_real
115 system.cpu[i].dcache_mon = dcache_mon
116
117 system.cpu[i].createInterruptController()
118 if options.l2cache:
119 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
120 else:
121 system.cpu[i].connectAllPorts(system.membus)
122
123 return system