1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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71 size=options.l2_size,
72 assoc=options.l2_assoc)
73
74 system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
75 width = 32)
76 system.l2.cpu_side = system.tol2bus.master
77 system.l2.mem_side = system.membus.slave
78
79 for i in xrange(options.num_cpus):
80 if options.caches:
81 icache = icache_class(size=options.l1i_size,
82 assoc=options.l1i_assoc)
83 dcache = dcache_class(size=options.l1d_size,
84 assoc=options.l1d_assoc)
85
86 # When connecting the caches, the clock is also inherited
87 # from the CPU in question
88 if buildEnv['TARGET_ISA'] == 'x86':
89 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
90 PageTableWalkerCache(),
91 PageTableWalkerCache())
92 else:
93 system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
94 system.cpu[i].createInterruptController()
95 if options.l2cache:
96 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
97 else:
98 system.cpu[i].connectAllPorts(system.membus)
99
100 return system