1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29# Configure the M5 cache hierarchy config in one place
30#
31
32import m5
33from m5.objects import *
34from Caches import *
35from O3_ARM_v7a import *
36
37def config_cache(options, system):
38 if options.l2cache:
39 # Provide a clock for the L2 and the L1-to-L2 bus here as they
40 # are not connected using addTwoLevelCacheHierarchy. Use the
41 # same clock as the CPUs, and set the L1-to-L2 bus width to 32
42 # bytes (256 bits).
43 if options.cpu_type == "arm_detailed":
44 system.l2 = O3_ARM_v7aL2(clock = options.clock,
45 size = options.l2_size,
46 assoc = options.l2_assoc,
47 block_size=options.cacheline_size)
48 else:
49 system.l2 = L2Cache(clock = options.clock,
50 size = options.l2_size,
51 assoc = options.l2_assoc,
52 block_size = options.cacheline_size)
53
54 system.tol2bus = CoherentBus(clock = options.clock, width = 32)
55 system.l2.cpu_side = system.tol2bus.master
56 system.l2.mem_side = system.membus.slave
57
58 for i in xrange(options.num_cpus):
59 if options.caches:
60 if options.cpu_type == "arm_detailed":
61 icache = O3_ARM_v7a_ICache(size = options.l1i_size,
62 assoc = options.l1i_assoc,
63 block_size=options.cacheline_size)
64 dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
65 assoc = options.l1d_assoc,
66 block_size=options.cacheline_size)
67 else:
68 icache = L1Cache(size = options.l1i_size,
69 assoc = options.l1i_assoc,
70 block_size=options.cacheline_size)
71 dcache = L1Cache(size = options.l1d_size,
72 assoc = options.l1d_assoc,
73 block_size=options.cacheline_size)
74
75 # When connecting the caches, the clock is also inherited
76 # from the CPU in question
77 if buildEnv['TARGET_ISA'] == 'x86':
78 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
79 PageTableWalkerCache(),
80 PageTableWalkerCache())
81 else:
82 system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
83 system.cpu[i].createInterruptController()
84 if options.l2cache:
85 system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
86 else:
87 system.cpu[i].connectAllPorts(system.membus)
88
89 return system