Searched refs:WR (Results 1 - 11 of 11) sorted by relevance

/gem5/src/systemc/tests/systemc/tracing/wif_trace/pct1/
H A Dmonitor.h54 sc_signal<bool>& WR )
55 : tx(TX), dout(DOUT), wr(WR)
/gem5/ext/drampower/src/
H A DMemCommand.cc87 int64_t WR = memSpec.memTimingSpec.WR; local
111 precharge_offset = B + WL + WR;
113 precharge_offset = B + WL + WR;
115 precharge_offset = B + WL + WR;
117 precharge_offset = B + WR; // + DQSS actually, but we don't have that parameter.
119 precharge_offset = B + WL + WR + 1;
121 precharge_offset = B + WL + WR + 1;
123 precharge_offset = B + WL + WR - 1;
145 return MemCommand::WR;
[all...]
H A DMemTimingSpec.cc67 WR(0),
104 WR = getParamValWithDefault("WR", 0);
H A DMemTimingSpec.h72 int64_t WR; member in class:Data::MemTimingSpec
H A DCAHelpers.cc62 } else if (type == MemCommand::WR) {
65 memTimingSpec.WR;
H A DMemCommand.h53 * 3. WR - Write
75 WR = 2, enumerator in enum:Data::MemCommand::cmds
147 "WR",
H A DCommandAnalysis.cc229 } else if (type == MemCommand::WR) {
273 end_write_op = latest_write_cycle + timeToCompletion(MemCommand::WR) - 1;
H A DCmdHandlers.cc98 printWarningIfPoweredDown("Command issued while in power-down mode.", MemCommand::WR, timestamp, bank);
99 // If command is WR - update number of writes and write cycle. Check
102 printWarning("Bank is not active!", MemCommand::WR, timestamp, bank);
H A DCmdScheduler.cc360 cmd.name = "WR";
532 memArchSpec.dataRate - 1 + memTimingSpec.WR;
535 memArchSpec.dataRate + memTimingSpec.WR;
/gem5/src/mem/
H A Ddrampower.cc91 timingSpec.WR = divCeil(p->tWR, p->tCK);
H A Ddram_ctrl.cc1113 // if so, wake up from power down to issue RD/WR burst
1169 // RD/WR burst commands to the same bank group.
1269 std::string mem_cmd = dram_pkt->isRead() ? "RD" : "WR";
1273 MemCommand::WR;
1858 // RD/WR or refresh commands
1976 // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled
1984 // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled

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