Searched refs:MISCREG_ICH_LRC0 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh877 MISCREG_ICH_LRC0, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc816 return MISCREG_ICH_LRC0;
4925 InitReg(MISCREG_ICH_LRC0)
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc703 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
1452 case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: {

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