Searched refs:MISCREG_ICC_BPR0_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc314 case MISCREG_ICC_BPR0_EL1: {
319 value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
1048 case MISCREG_ICC_BPR0_EL1: {
1070 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1933 bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
2549 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
2562 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1;
/gem5/src/arch/arm/
H A Dmiscregs.hh682 MISCREG_ICC_BPR0_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2403 return MISCREG_ICC_BPR0_EL1;
4519 InitReg(MISCREG_ICC_BPR0_EL1)

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