Searched refs:MISCREG_ICC_AP1R0_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc123 case MISCREG_ICC_AP1R0_EL1: {
128 return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1);
745 case MISCREG_ICC_AP1R0_EL1:
750 setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
/gem5/src/arch/arm/
H A Dmiscregs.hh687 MISCREG_ICC_AP1R0_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2417 return MISCREG_ICC_AP1R0_EL1;
4535 InitReg(MISCREG_ICC_AP1R0_EL1)

Completed in 30 milliseconds