Searched refs:CacheLineSize (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/dev/pci/ | ||
| H A D | PciDevice.py | 69 CacheLineSize = Param.UInt8(0, "System Cacheline Size") variable in class:PciDevice |
| H A D | device.cc | 97 config.cacheLineSize = htole(p->CacheLineSize); |
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