Searched hist:6025 (Results 1 - 10 of 10) sorted by relevance

/gem5/src/arch/alpha/
H A DSConsopts6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants
H A Dev5.hh6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants
H A Dtlb.cc6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants
/gem5/src/arch/riscv/insts/
H A Damo.hh12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
H A Damo.cc12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
H A DSConscript12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
/gem5/src/arch/riscv/isa/
H A Dincludes.isa12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
/gem5/src/arch/riscv/isa/formats/
H A Damo.isa12323:55d08b81ff39 Fri Nov 10 00:23:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
/gem5/tests/
H A DSConscript6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants
/gem5/
H A DSConstruct6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants

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