Searched hist:3102 (Results 1 - 5 of 5) sorted by relevance

/gem5/src/python/m5/
H A D__init__.py3102:225b76c8ac68 Mon Sep 04 20:14:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> More Python hacking to deal with config.py split
and resulting recursive import trickiness.
H A Dparams.py3102:225b76c8ac68 Mon Sep 04 20:14:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> More Python hacking to deal with config.py split
and resulting recursive import trickiness.
H A DSimObject.py3102:225b76c8ac68 Mon Sep 04 20:14:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> More Python hacking to deal with config.py split
and resulting recursive import trickiness.
/gem5/src/sim/
H A Dmain.cc3102:225b76c8ac68 Mon Sep 04 20:14:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> More Python hacking to deal with config.py split
and resulting recursive import trickiness.
/gem5/src/mem/cache/
H A Dcache.cc11745:3102db8903f5 Mon Dec 05 16:48:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> mem: Ensure InvalidateReq is considered isForward by MSHRs

This patch fixes an issue where an MSHR would incorrectly be perceived
to provide data to targets arriving after an InvalidateReq. To address
this the InvalidateReq is now treated as isForward, much like an
UpgradeReq that did not hit in the cache.

Change-Id: Ia878444d949539b5c33fd19f3e12b0b8a872275e
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>

Completed in 107 milliseconds